Design a real chip in your browser.

From an idea to a layout, in four steps.

Each step runs real tools and shows you a real result. These pictures come from designs run in the lab.

1. 1

   Describe it, or write it

   Tell Nelix Agent what you want and it drafts a specification, the design and a test with you. Or write the SystemVerilog yourself. Nothing reaches your project until you approve it.

   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       count <= 8'd0;
       en    <= 1'b0;
     end else begin
       en <= 1'b1;
       if (en) count <= count + 8'd1;
     end
   end
   assign done = (count == 8'd32);

   The counter from the first guided project.

2. 2

   Simulate

   Run a test against the design and watch every signal. When a test fails, the lab shows what was expected, what happened, and where.

   That counter in simulation: held at 0 in reset, then counting. Recorded from a real run.

3. 3

   Synthesize

   Turn the code into logic gates and see the circuit it became. It is the quickest way to check that the tools understood what you meant.

   The same counter, as the synthesis tool drew it: registers, an adder and a comparison.

4. 4

   Build the chip

   Place and route the gates into a layout: floorplan, placement, clock tree, routing, timing and the final checks. The lab shows each phase as it happens, then the measured result.

   • Prepare
   • Floorplan
   • Placement
   • Clock tree
   • Routing
   • Timing
   • Sign-off
   What a build constructs: a die, rows of placed cells, a power grid and pins. A diagram.