Open-source notices

Nelix Chip Design Ltd. · Last updated 30 October 2026

Nelix Silicon Lab is built on open-source software and open process design kits. We are grateful to their authors. Each one is used under its own licence, as published by its project and listed below. The programs run on our servers and are not handed out; the source code of each is available from its project. The process kits are different: a layout you download from the lab (the GDS file in a download or in a tapeout package) contains the process kit's own standard-cell layouts, and the layout of the kit's memory block when your design uses one. Those cell layouts remain under the kit's licence listed below. Keep this notice, and the licence it names, with any layout you pass on.

Chip design flows

OpenLane 2 (build flow for SKY130 and GF180MCU): Apache License 2.0.

LibreLane (build flow for IHP SG13G2): Apache License 2.0.

OpenROAD Flow Scripts (build flow for ASAP7): BSD 3-Clause License.

Synthesis, place and route, timing and sign-off

Yosys (synthesis): ISC License.

OpenROAD (floorplan, placement, clock tree, routing): BSD 3-Clause License. It includes OpenSTA (timing analysis), under the GNU General Public License version 3.

Magic (layout and design-rule checks): BSD-style licence of the Regents of the University of California.

Netgen (layout versus schematic): GNU General Public License version 1.

KLayout (layout viewing and design-rule checks): GNU General Public License.

Simulation and verification

Icarus Verilog (simulation): GNU General Public License version 2.

GHDL (VHDL simulation, and reading VHDL for synthesis): GNU General Public License version 2 or later.

Verilator (lint and coverage): GNU Lesser General Public License version 3, or the Perl Artistic License 2.0.

cocotb (testbenches): BSD 3-Clause License.

SymbiYosys (formal checks): ISC License.

Z3 (solver used by the formal checks): MIT License.

Analog Lab

ngspice (circuit simulation): BSD 3-Clause License.

Xschem (schematics): GNU General Public License version 2.

Process design kits (their cell layouts are inside the layouts you download)

GlobalFoundries GF180MCU (gf180mcuD: standard cells gf180mcu_fd_sc_mcu7t5v0 and mcu9t5v0, primitives and I/O cells; open_pdks build 0fe599b2): Apache License 2.0. Copyright 2022 GlobalFoundries PDK Authors.

IHP SG13G2 (standard cells sg13g2_stdcell, primitives and I/O cells; IHP-Open-PDK c4b8b4e5): Apache License 2.0. Copyright 2023-2025 IHP PDK Authors. Some other files of that kit (device models under the Educational Community License 2.0, layout and field-solver scripts under the GNU General Public License version 3, I/O documentation under the GNU Affero General Public License version 3) are used only on our servers and are not part of any download.

ASAP7 (cells asap7sc7p5t, version 1.7, as bundled with OpenROAD Flow Scripts; a predictive kit for learning; no foundry makes chips in it): BSD 3-Clause License. Copyright 2020 and 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State University. Its conditions: keep that copyright notice, the list of conditions and the disclaimer with any copy, and do not use the names of the copyright holders or contributors to endorse or promote products. Its KLayout rule deck is under the BSD 2-Clause License.

The Analog Lab uses a second copy of the same three open kits at other revisions (open_pdks 1689ac3f, IHP-Open-PDK a49358cc), under the same licences.

The Apache License 2.0 is at apache.org/licenses/LICENSE-2.0; the BSD 3-Clause License at opensource.org/license/bsd-3-clause.

Memory blocks (SRAM macros)

SKY130 SRAM macros (sky130_sram_macros: OpenRAM blocks of 1 and 2 kilobytes, built on SkyWater's sky130_fd_bd_sram bitcells): Apache License 2.0, as published by the OpenRAM project and SkyWater. The installed files carry no licence header of their own.

ASAP7 memory outlines (fakeram7, made by FakeRAM 2.0 and shipped with OpenROAD Flow Scripts): these files state no licence. They are used only as outlines (black boxes); no memory layout from them is in any downloaded layout.

Code editor

code-server: MIT License.

Code - OSS (the open-source core of Visual Studio Code): MIT License.

EditorConfig and indent-rainbow extensions: MIT License.

Chip pictures and 3D views

Parts of the 3D view are adapted from the render tools of the npu-2x2-int4-16bit project and from GDS2glTF, both under the Apache License 2.0; layer colours come from OpenROAD Flow Scripts (BSD 3-Clause). Their licence files are kept with our code, and our changes are marked in it.

Process Lab

The Process Lab uses its own set of open-source components (among them ViennaPS, DEVSIM, NumPy, SciPy, Three.js, KaTeX and the Geist fonts) under the MIT, Apache 2.0, BSD and SIL Open Font licences. Each is listed with its version and conditions in the Process Lab's licence notes.

Names and trademarks

The names of these projects, process kits and companies belong to their owners. Their use here describes what the lab runs and does not mean they endorse Nelix.

Questions

If you think a notice here is missing or wrong, write to info@nelix.io and we will correct it.