Design a real chip in your browser.

1. 01

   Describe it, or write it

   Tell Nelix Agent what you want. It drafts a specification, the design and a test with you. Or write the SystemVerilog yourself. Nothing reaches your project until you approve it.

   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       count <= 8'd0;
       en    <= 1'b0;
     end else begin
       en <= 1'b1;
       if (en) count <= count + 8'd1;
     end
   end
   assign done = (count == 8'd32);

   The counter from the first guided project.

2. 02

   Simulate

   Run a test and watch every signal. When it fails, the lab shows what was expected, what happened, and where.

   That counter in simulation: held at 0 in reset, then counting. Recorded from a real run.

3. 03

   Synthesize

   Turn your code into logic gates and see the circuit it became. The quickest way to check the tools understood what you meant.

   The same counter, as the synthesis tool drew it: registers, an adder and a comparison.

4. 04

   Build the chip

   Place and route the gates into a layout. Watch each phase as it runs, then read the measured result.

   • Prepare
   • Floorplan
   • Placement
   • Clock tree
   • Routing
   • Timing
   • Sign-off
   What a build constructs: a die, rows of placed cells, a power grid and pins. A diagram.

1. 01Your first chipTake a working counter through the whole flow.
2. 02Find the bugMake a failing test pass by fixing one line.
3. 03Finish the designWrite the missing logic of a PWM output.
4. 04State machineDetect a bit pattern, state by state.
5. 05UART transmitterBuild a real serial protocol.

Nelix Agent may only state what the tools measured, and it names the run. It proposes; you decide. Nothing is written to your project until you accept it.

How the agents are configured →

Nelix Chip Design builds the lab to grow chip design talent everywhere.