Supported processes

The four processes you can build for, what each is for, and which can become a real chip.

StudentEngineer 4 min read · Updated 2026-10-30

        On this page
        The four processesASAP7 is for learning onlyTypical public valuesHow each is builtComparing processesLimits on every process
      

A process is the way a factory (a foundry) makes chips. You choose one when you create a project on the New project page. Each project builds for one process; to try another, use Change process on the project's Overview, which makes a copy for the new process and leaves your RTL and tests as they are.

The four processes#

Process	Status	What it is	What it is for	Real chips
SKY130	Ready	Open 130 nm CMOS process from SkyWater, 1.8 V core	Learning and real low-cost chips. The lab's original process	Tiny Tapeout (SKY130), ChipFoundry chipIgnite
GF180MCU	Ready	Open 180 nm CMOS process from GlobalFoundries, 5 V cells	Robust 5 V digital logic at tens of MHz	wafer.space, Tiny Tapeout (GF180)
IHP SG13G2	Preview	Open 130 nm SiGe BiCMOS process from IHP, 1.2 V core	Digital designs for a European research route; room for radio and fast analog later	Tiny Tapeout (IHP), IHP open multi-project wafer runs
ASAP7	Learning only	Predictive 7 nm FinFET kit from Arizona State University and Arm, about 0.7 V	Seeing what an advanced node does to area, speed and power	None. It cannot be manufactured

"Preview" is IHP's own label for its open kit: it works, and its rules and cells may still change between releases.

All three open kits are preview kits upstream. SkyWater and GlobalFoundries call SKY130 and GF180MCU an experimental preview, not intended for production, and IHP calls SG13G2 a preview. "Ready" here means the lab's flow for that kit is complete and has passed the lab's release gate. It is not a silicon or yield guarantee. What the lab has shown on each process, with build ids, is on Qualification envelope.

ASAP7 is for learning only#

ASAP7 describes a plausible 7 nm process, but no factory makes it. Its builds have routing checks only: there is no sign-off design-rule check (DRC) and no layout-versus-schematic check (LVS), so the Sign-off step on the build bar is grey. Even when an ASAP7 build passes, the Overview's Export / tapeout step says "Learning only: not made into chips" and Design review's Is it ready to make? answers "No". Use it to compare, never for a design meant to become a chip. Since 2026-10-29 an ASAP7 build also keeps its synthesized netlist, the synthesis cell report, the final timing report and the extracted parasitics (SPEF) with the build's files, so the Compare page can show area after synthesis and the chip report can say which extraction the timing used (builds made before that date have none of these).

Typical public values#

For orientation only. Your own build's measured numbers always win.

	SKY130	GF180MCU	IHP SG13G2	ASAP7
Feature size	130 nm	180 nm	130 nm	7 nm (predictive)
Core supply	1.8 V	5 V (this library)	1.2 V	about 0.7 V
Metal layers	local interconnect + 5	5 (gf180mcuD)	5 thin + 2 thick	9
Standard cells	sky130_fd_sc_hd	gf180mcu_fd_sc_mcu7t5v0	sg13g2_stdcell	asap7sc7p5t

How each is built#

Process	Build tool	Checks	DFT (scan test)
SKY130	OpenLane	DRC (Magic and KLayout), LVS, antenna	Stuck-at, teaching level
GF180MCU	OpenLane	Magic DRC, LVS, antenna. KLayout DRC does not run in the build. GlobalFoundries' KLayout deck runs only when you ask for it from the build report, and its density and antenna rules are left out	Stuck-at, teaching level
IHP SG13G2	LibreLane	DRC (Magic and KLayout), Netgen LVS, antenna. A KLayout LVS cross-check is planned	Stuck-at, teaching level
ASAP7	OpenROAD flow	Routing checks only	Not supported: its cell models are not in the lab's tool image

"Stuck-at, teaching level" means the V&V page's DFT check runs a stuck-at ATPG on the build's netlist and passes at 90 % coverage. A normal build has no scan chain; V&V → DFT: scan chain built into the chip builds one into a separate -scan project on SKY130, GF180MCU and IHP SG13G2 and checks it in the layout (on 30 October 2026: 57 of 57 scan flip-flops, DRC/LVS/antenna clean, ATPG 97.8 / 97.0 / 96.8 %). See Manufacturing boundary.

The same design needs a longer clock on a slower process. The MAC-8 starter uses 15 ns on SKY130 and 30 ns on GF180MCU.

Comparing processes#

Compare builds puts finished builds side by side: area, timing, power and more, with one colour per process. Tick builds in a Runs list and choose Compare selected builds, or open the Compare tab of a project.

Limits on every process#

Digital standard cells only, one clock, no analog blocks, no pads. Storage is in flip-flops, or in the process kit's own memory blocks (SRAM; see the in-lab guide Memory blocks, /app/guide/memory). A clean build here is a layout, not a tape-out: each shuttle applies its own checks.

Signed in, each process has a longer page under Processes in the lab (/app/processes).

SKY130 and its standard cellsThe manufacturing process the lab builds for: what it is, what it offers and what it does not.
Creating projectsCreate a project from a starter, switch between projects, and delete one.
Progress marks and comparing runsSee how far every project has got, lay two simulations over each other, and set targets the lab checks for you.
Qualification envelopePer process, the largest design the lab has built clean (with its build id), the tool versions and limits, the class of each rule deck, and the claims the lab does not make.

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