Toolchain overview and versions
The tools behind each stage, their versions, and the command each stage runs.
On this page
VersionsSimulate and Synthesize (every process)Build the chip, by processWhat each stage runsWhat each tool does in the buildReading tool errorsChecking your code strictlyOne article per toolHow versions are kept the sameThe lab is built on open-source tools. Each stage runs in its own container on the Nelix server.
Versions#
Simulate and Synthesize are the same on every process. Build the chip uses the flow of the project's process, which is set in config/project.toml ([asic] pdk = ...).
Simulate and Synthesize (every process)#
| Stage | Tool | Version |
|---|---|---|
| Simulate | Icarus Verilog | 12.0 |
| Simulate | cocotb | 2.1.0 |
| Simulate | Python | 3.12 |
| Synthesize | Yosys | 0.33 |
| Simulate and Synthesize image | Verilator | 5.020 |
| Simulate (VHDL projects) | GHDL | 4.1.0 (VHDL-2008) |
Build the chip, by process#
| Process | Flow | Yosys | Verilator (lint) | Magic | KLayout | Netgen |
|---|---|---|---|---|---|---|
| SKY130 (sky130A) | OpenLane 2.3.10 | 0.46 | 5.018 | 8.3.489 | 0.29.4 | 1.5.278 |
| GF180MCU (gf180mcuD) | OpenLane 2.3.10 | 0.46 | 5.018 | 8.3.489 | 0.29.4 | 1.5.278 |
| IHP SG13G2 (ihp-sg13g2) | LibreLane 3.0.14 | 0.62 | 5.044 | 8.3.623 | 0.30.7 | 1.5.316 |
| ASAP7, learning only (asap7) | OpenROAD flow scripts (ORFS) 26Q3-705-gecb3cfdeb | 0.68+post | not part of this flow | not part of this flow | 0.30.12 | not part of this flow |
OpenROAD is the version shipped inside each flow. VHDL projects build with OpenLane's VHDL flow (Yosys 0.46 with the GHDL plugin).
- GF180MCU: OpenLane skips the KLayout design-rule check on this process; Magic's check still runs.
- ASAP7 is a teaching process: it cannot be manufactured, and it has no sign-off DRC or LVS (only the router's own checks). Its timing numbers are in picoseconds (ps), not nanoseconds.
What each stage runs#
| Stage | Command the lab runs |
|---|---|
| Simulate | make WAVES=1 in the project folder |
| Synthesize | yosys -l reports/synth.log synth.ys |
| Build the chip, SKY130 or GF180MCU | OpenLane on openlane/config.json |
| Build the chip, IHP SG13G2 | LibreLane on openlane/config.json |
| Build the chip, ASAP7 | The OpenROAD flow scripts for the asap7 platform, with the design name, files and clock read from openlane/config.json (the clock period is still written in ns there) |
| Simulate, VHDL project | GHDL on the files named in the Makefile (see VHDL projects) |
What each tool does in the build#
| Tool | Job |
|---|---|
| Yosys | Synthesis: code to gates |
| OpenROAD | Floorplan, placement, clock tree, routing and timing |
| Magic and KLayout | Writing the layout and checking it against the design rules (on ASAP7, KLayout only writes the layout) |
| Netgen | Comparing the layout with the netlist |
Reading tool errors#
| Tool says | Meaning |
|---|---|
| Icarus: a syntax error with a file and line | A mistake in the code at that line |
Icarus: Unknown module type | A module is missing or its name is misspelled |
cocotb: AssertionError | The test disagrees with the design. The message holds the expected and seen values |
| Yosys: a latch is inferred | An always_comb block does not assign an output on every path |
| OpenLane: setup violations | A path is slower than the clock allows |
Checking your code strictly#
Verilator is a strict reader of code, and the build runs its lint as a first step. See Verilator.
One article per tool#
How versions are kept the same#
Each stage runs in a container built from a fixed image, so every run of every user gets the same tool versions. A result does not depend on what is installed on your computer, and a run today uses the same tools as a run last week.
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