Final artefacts and handoff

A build that passes produces a layout and the evidence about it.

What you get#

What a passing build establishes#

• The design was synthesized, placed and routed for the project's process.
• Timing met the constraints given, at the corners the build checked.
• The layout passed the design-rule and layout-versus-schematic checks in the open kit.

What it does not establish#

The lab enforces part of this on the project's Tapeout page: a build that misses timing is never offered for a package, and the package and the tapeout review are refused while a required readiness check fails or did not run, unless a waiver (the check, a reason, who approved it, the date) is recorded. Waivers travel in the package and in the reproducibility bundle. Each process page and the sign-off checklist show What the lab checks for <process>: the rule decks, LVS, antenna, density, timing and extraction corners the lab really covers. See Tapeout gates and waivers.

A real handoff also needs, among other things:

• Verification you can stand behind. One passing test is not a verification plan. Real projects measure coverage and review what was never tested.
• Constraints that describe the real surroundings. The timing of signals arriving from outside the chip, and the loads the outputs drive.
• Design for test in the layout. The lab's DFT check runs stuck-at ATPG on your netlist at teaching level, but the flow does not build a scan chain into the layout.
• Pads and a padframe. A design here ends in plain pins on the die edge. A packaged chip needs pads and protection against static discharge.
• The foundry's own checks. A manufacturer or shuttle programme runs its own rule decks and has its own submission requirements, which go beyond the open kit.
• Power analysis under realistic activity.

Manufacturing boundary sets out, on one page, what the lab does on the way to a real chip, at which level, and what it leaves to you. In short:

• DFT and bring-up run at teaching level: stuck-at ATPG on the netlist, and a simulated power-on of the gate-level netlist.
• Test structures, pads, packaging and board design are not offered.
• Testing real chips, reliability and production testing, and IP and licence checks are not offered either.

What the lab is for#

It teaches the whole flow with real tools and real results, and lets engineers explore a design's area and timing quickly. Treat a layout from the lab as a completed exercise or an early study, not as a product.

If you want to manufacture#

Open shuttle programmes for the sky130 process have existed, each with its own rules, templates and schedule. Start from the programme's current requirements, and expect to rework the design to fit its frame.