Design rules
The limits a factory places on shapes, why they exist, and how they are checked.
A factory prints a chip in layers, with light and chemistry. There are limits to how small and how close together it can print reliably. Design rules state those limits. A layout that breaks one may not work, or may work on some chips and not others.
Kinds of rule#
| Rule | Says | Why |
|---|---|---|
| Minimum width | A wire must be at least this wide | A thinner wire may break |
| Minimum spacing | Two shapes on a layer must be at least this far apart | Closer shapes may merge into a short |
| Enclosure | A via must be surrounded by this much metal | So the connection survives misalignment between layers |
| Minimum area | A shape must be at least this large | Very small shapes may not print |
| Density | Each region must contain a certain share of metal | Even density keeps the layers flat during polishing |
| Antenna | A wire attached to a gate must not collect too much charge | The charge can destroy the gate during manufacturing |
Why fill cells exist#
The density rules are why a finished layout has cells and metal with no function. Empty rows are filled so every region meets its density. The picture on a lab share page leaves these out, so the working logic is visible.
Who obeys the rules#
You do not draw shapes, so you do not apply these rules by hand. The standard cells already obey them, and the router is built to obey them. The design-rule check at the end confirms it.
When a rule is broken#
A violation after a build is usually a symptom, not a cause: the router ran out of room and left something illegal. The fix is usually more space, a larger die or a lower placement density, not a change to the rule.
In this lab#
The build runs the design-rule check with two tools, and the chip report shows the count. nelix ai drc asks a specialist to read the result. The rules themselves are those of the open sky130 kit.
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