Timing constraints

The tools cannot know how fast your design must run. You tell them, with constraints. Timing is then judged against what you asked for.

The clock constraint#

The one every design needs: which port is the clock, and what its period is.

create_clock -name clk -period 10.0 [get_ports clk]

This is the whole of constraints/clock.sdc in the Blank starter. It says: there is a clock on the port clk, with a period of 10 ns. The format is SDC, the industry standard.

Where it lives in a project#

Keep all three in step when you change the clock.

Your own constraints in the build. A chip build on SKY130, GF180MCU or IHP applies constraints/clock.sdc itself in synthesis and timing analysis (OpenLane's PNR_SDC_FILE and SIGNOFF_SDC_FILE), instead of the flow's default file made from CLOCK_PERIOD. Everything in the file counts: the clock period, set_input_delay / set_output_delay, set_clock_uncertainty, set_false_path, set_multicycle_path, set_max_fanout, set_load. Before a build is queued the lab checks the file: only plain timing constraints with sensible numbers are accepted; a line such as exec, source, set, [expr …] or any command the lab does not know is refused with a plain message and nothing runs. A 4 ns clock on a design that only meets 10 ns gives a build that finishes with timing not met, as it should. The build's Conditions panel then says Your own constraints file. ASAP7 (learning only) keeps the lab's own clock-only file. Simulation V&V also shows whether your file would be accepted, before you build.

Inputs and outputs#

A signal arriving from outside the chip does not arrive at the start of the clock. It has already used part of the period getting there. An output must likewise be ready early enough for whatever reads it. Constraints on input and output delay describe this.

The MAC-8 specification mentions the effect: its inputs "arrive from outside the chip partway through" the clock, which is part of why the multiply and add struggled to fit in 10 ns.

Choosing a period#

Choose from what the design is for, not from what happens to pass. Then build, and read the result.

What the build tells you#

The build measures every path against the constraints and reports the worst margin, the slack, for each corner. Positive slack: met. Negative: not met.