Get your chip made

The four shuttle routes that take a design from this lab to real silicon, which ones fit your process, and how to prepare a submission package.

StudentEngineer 3 min read · Updated 2026-10-30

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        Your designFive steps to siliconFour routesA submission package for your projectWhat Nelix does and does not do
      

A passed chip build in this lab is a layout that could be made in a real fab. Get your chip made shows how to get there through a shuttle: a run where many designs share one wafer, so each pays only for its own area.

Open it from Get your chip made in the left sidebar.

Your design#

The top of the page shows your latest finished chip build: the project, its process, the date, timing, die size and each sign-off check (clean, fails or not run). See the report or See what to fix opens its build report. If you have no finished build yet, the page says Build a chip first.

Five steps to silicon#

Design passes: every check clean.
Choose a route: a shuttle that takes your process.
Prepare the files: GDS, pins and the partner's template.
Submit: to the partner, before its deadline.
Chips arrive: then you test them.

Four routes#

Route	Best for	Processes
Tiny Tapeout	Learners and hobbyists: a small tile on a shared chip	SKY130, GF180MCU, IHP SG13G2
wafer.space	Bigger designs and small companies: your own die, 1,000 per slot	GF180MCU
IHP Open-Silicon MPW	Open-source designs: 40 bare dies	IHP SG13G2
ChipFoundry chipIgnite	Private designs: 100 packaged chips and an evaluation board	SKY130

Routes that take your latest build's process are marked Fits your design. Each card's Size, pins, template and dates link opens that route's own page with its prices, sizes, rules and sources. The partner facts show the date they were confirmed with each partner; prices and slots change, so check with the partner before you plan around them.

ASAP7 is a learning-only process: no fab makes chips in it, so no route takes an ASAP7 build. To get a chip made, build it in SKY130, GF180MCU or IHP SG13G2.

A submission package for your project#

Each project has a Tapeout page (the project's Project menu, under Share & ship, or /app/projects/<project>/tapeout). There you choose a target shuttle for the project's process, see a readiness list against that target, and make a draft submission package from your latest passed build. You can also send the package to a reviewer (a teacher or mentor) for a tapeout review once the project's Sign-off gate is approved.

The page only uses a passed build that also meets its clock; a build that is Built, timing not met is skipped, and the page says so ("BLD-… passed its layout checks but misses its clock by 5.61 ns, so it cannot be taped out"). While a required readiness check fails or did not run, Download a draft package and Make the package and ask for review are refused ("Tapeout package blocked: N checks fail or did not run") unless a waiver is recorded for each. A table What the lab checks for <process> lists, per process, which rule decks run and which checks are not available. Details: Tapeout gates and waivers.

If the design changed after the passed build, the Tapeout page and the Share page say so: build the chip again first, so the package, the public page and the certificate show the design as it is now.

A saved package contains the GDS layout file, so downloading it needs a plan with GDS download (Professional and up). See Plans and allowances.

What Nelix does and does not do#

The open kits are preview kits. SkyWater and GlobalFoundries call SKY130 and GF180MCU an experimental preview, and IHP calls SG13G2 a preview. A clean build here is not a silicon or yield guarantee, and each shuttle runs its own precheck. Manufacturing boundary lists what the lab does on the way to a chip and what it leaves to you: DFT, bring-up, pads, packaging and testing.

Nelix does not submit designs for you yet. Nelix Tapeout, where Nelix takes your signed-off design to a shuttle and does the partner paperwork, is coming soon. Until then you submit to the partner yourself.

Efabless, which ran the earlier open shuttles, shut down in 2025. Do not plan around Efabless or the old Google Open MPW shuttles.

Build results: Passed, timing not met, FailedWhat the green, amber and red labels on a chip build mean.
Final artefacts and handoffWhat a finished build gives you, and the gap between a checked layout and a design ready to manufacture.
Supported processesThe four processes you can build for, what each is for, and which can become a real chip.
Manufacturing boundaryOne place that says what the lab does on the way to a real chip, at what level, and what it leaves to you, the shuttle or the foundry.

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