Yosys

The synthesis tool: the script the Synthesize stage runs, step by step, and the two versions in use.

Engineer 2 min read · Updated 2026-10-24

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        Two versionsThe scriptThe cell namesCommon messagesWhat its schematic looks like
      

Yosys is an open-source synthesis tool. It reads RTL and produces a netlist of gates.

Two versions#

Where	Version	Maps onto
The Synthesize stage	0.33	Generic gates
Inside Build the chip, SKY130 and GF180MCU	0.46, as part of OpenLane 2.3.10	The process's standard cells
Inside Build the chip, IHP SG13G2	0.62, as part of LibreLane 3.0.14	The process's standard cells
Inside Build the chip, ASAP7	0.68+post, as part of the OpenROAD flow scripts	The ASAP7 standard cells

A design must be accepted by the Synthesize stage and by the build. That is one reason the lab's coding standard is conservative.

The script#

The Synthesize stage runs yosys -l reports/synth.log synth.ys. This is the starter's synth.ys, with what each line does.

text

read_verilog -sv rtl/top.sv
hierarchy -check -top top
proc
opt
fsm
opt
memory
opt
write_verilog -noattr reports/top_synth.v
techmap
opt
stat
write_verilog -noattr reports/top_gates.v

Command	What it does
`read_verilog -sv`	Reads the design as SystemVerilog
`hierarchy -check -top top`	Confirms `top` exists and every module it uses is defined
`proc`	Turns `always` blocks into flip-flops and logic
`opt`	Simplifies: removes unused logic, merges duplicates
`fsm`	Recognises and optimises state machines
`memory`	Handles arrays
`write_verilog reports/top_synth.v`	Writes the block-level netlist. The schematic is drawn from this one
`techmap`	Breaks blocks such as adders into simple gates
`stat`	Prints the cell count
`write_verilog reports/top_gates.v`	Writes the gate-level netlist

The cell names#

Name	Is
`$_AND_`, `$_OR_`, `$_XOR_`, `$_NOT_`, `$_MUX_`	Simple gates
`$_DFF_PN0_`	A flip-flop: rising clock edge, active-low reset to 0
`$_DFFE_PN0P_`	The same, with an enable

Common messages#

Message	Meaning
`Module \top not found`	There is no module named `top` in `rtl/top.sv`
`Latch inferred for signal`	A combinational block does not assign that signal on every path
`Multiple conflicting drivers`	Two blocks assign the same signal
`syntax error`	A construct Yosys 0.33 does not accept, or a real syntax error

A line reading No latch inferred for signal is good news: Yosys checked and found none.

What its schematic looks like#

The Blank starter as the synthesis tool draws it: one register with a clock, an asynchronous reset, an input and an output.

SynthesisHow code becomes logic gates, and what to look for in the result.
Synthesis failuresThe design simulates and the Synthesize stage rejects it, or produces something unexpected.