Simulate
Run the test against your design and read the result.
Simulation answers one question: does the design behave correctly? It runs the test in tb/test_top.py against the design in rtl/top.sv.
Run it#
From Overview: on the Simulate card, press Simulate. The card shows the run, then its result. The Log tab in the panel on the right shows the output as it happens.
From the Workspace terminal:
cd ~/project/mychip
nelix testBoth start the same run. The last lines of the output say whether the test passed and give the run its id, such as TST-20261005-0011.
What a first run looks like#
A new starter passes without any change. On MAC-8 the test multiplies pairs of signed 8-bit numbers and checks the running total, acc, after each one. A pass means every check in the test held.
Run the simulation again each time you change the design or the test. Each run is saved with its own id.
The result#
| Result | Meaning | What to do |
|---|---|---|
| Passed | The test finished and every check held | Open the waveform, then go on to Synthesize |
| Failed | A check did not hold, or the tool reported an error | Read the card, then see When a run fails |
| Timed out | The time limit stopped the run | Follow the next step on the card. A timeout alone is not a reason to edit the design |
Limits#
A simulation may run for up to 5 minutes. See Compute limits.
How it works#
The lab runs your test with cocotb, a Python test framework, on the Icarus Verilog simulator. See Verification for how to write a good test. Other test styles (New project → Test with): a Verilog testbench, C++ with Verilator, a SystemVerilog testbench (classes, constrained random, assertions; Verilator 5.044 with the z3 solver) and a UVM testbench (Accellera UVM on Verilator 5.052, about 11 minutes per Simulate); see the SystemVerilog the lab runs.
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