Choosing FPGA or ASIC
The two ways to turn a digital design into hardware, and which one this lab supports today.
The same RTL can become hardware in two ways.
The difference#
| FPGA | ASIC | |
|---|---|---|
| What it is | A chip that already exists, whose logic you configure | A chip manufactured for your design |
| Time to working hardware | Minutes | Months |
| Cost to try an idea | The price of a board | A manufacturing run |
| Can it be changed afterwards | Yes, as often as you like | No |
| Speed, power and cost per chip | Worse | Better, at volume |
| Good for | Prototypes, teaching, small volumes | Products at volume, and learning how chips are made |
What this lab supports#
A project's settings record this: target = "asic" and pdk = "sky130A" in config/project.toml.
What that means for you#
- You learn the ASIC flow end to end: synthesis, floorplanning, placement, clock tree, routing, timing and layout checks. Most courses stop at simulation.
- Your layout is real, and it is not a manufactured chip. The lab produces a layout file that has passed its own checks. Sending a design to be manufactured needs more than that. See Final artefacts and handoff.
- Your RTL carries over. Code written to the lab's RTL coding standard is ordinary synthesizable SystemVerilog. The same design can be taken to an FPGA with that vendor's tools, outside the lab.
If you need an FPGA#
Use the lab to write and verify the design, then take rtl/top.sv to your FPGA vendor's tools. The simulation and the test are independent of the target.
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