"Benchmarks: real designs through the lab"

This page exists so that anyone can check the lab against designs they did not write. The set is the one LiveHD (University of California, Santa Cruz, MASC group; BSD 3-Clause; https://github.com/masc-ucsc/livehd) publishes results for, because their numbers are public and independent of this lab: the three DINO CPUs, the 46-block CVA6 corpus and the 122 CORE-ET blocks of their manifests (commit 403a9e9, 29 October 2026), plus the PicoRV32 the lab already measured. LiveHD's authors do not endorse this lab; their measurements are theirs, and the lab reports only what it measured here.

How a row is made. A script on the lab's own server (bench/bench_livehd.py, run on the test account at the lowest priority, one build at a time, never while a student has a build queued) imports the design through the lab's ordinary Import from GitHub page (the repository's own branch and folder, the design's own top module and clock port), builds it once on SKY130 at the lab's defaults, runs the V&V rows lint, equivalence, DFT, CDC and power-on, reads every number from the lab's results store, and then removes the project's openlane/runs folder (the results store keeps the reports). A failed build is published as failed with its reason. No design is patched; a design that needs a lab change to build is a lab bug, listed below, not a reason to touch the design.

At a glance#

Every chart below is drawn from the lab's own measured runs; hover a bar or a dot to see the run behind it.

Status on 31 October 2026 (third pass, 10:40–13:20 UTC)#

The first night found three lab limits; the second pass fixed them and built the first two blocks through the new Slang build path (on for everyone since 31 October 2026): the chip build is fed Slang's elaboration of the SystemVerilog instead of the files themselves (see Seeds, proof limits, equivalence…).

Third pass (test account with free disk space). Both blocks were measured again with the clock constraint aligned, and the lab now chooses the reader automatically (on for everyone since 31 October 2026): before each chip build the flow's own Yosys is asked whether it can read the files; minion_tlb was refused (minion_pkg.sv:1627: syntax error, quoted in the build log) and built through Slang, the plain MAC-8 reference on all four processes was read and built from its own files. minion_tlb BLD-20261031-0056/0064: PASSED, timing met (10 ns clock on clk_i, setup slack 0.208 ns), DRC/LVS/antenna 0, lint clean, CDC pass (the check reads the kept elaboration), equivalence still REFUTED-unsupported (flip-flops on both clock edges), bring-up fail (an output still X after reset), DFT error (ATPG reported no coverage). CVA6 alu BLD-20261031-0061: built end to end (22,666 cells) but sign-off failed on 5 antenna violations; equivalence PROVEN-full like for like (65 signals), CDC pass (combinational), bring-up pass, lint 26 Verilator warnings. Timing of a combinational block is reported as unconstrained, which is correct.

What the two rows below show. minion_tlb builds end to end through Slang (7,591 cells, DRC 0, LVS 0, antenna 0; lint clean); its equivalence row is REFUTED-unsupported because the design clocks flip-flops on both edges, which the lab's engines do not prove; the CDC row cannot read the package with the flow's old reader (a follow-up: read the Slang elaboration when the build was through Slang); bring-up finds an output still X after reset. CVA6 alu builds through LiveHD's cva6_alu_export wrapper with the cv64a6_imafdc_sv39 configuration after the runner fetched popcount, lzc and cf_math_pkg the elaboration named as missing (22,666 cells, DRC 0, LVS 0) and fails sign-off on 5 antenna violations; its V&V rows did not run because the test account had used its 60 checks of the day. Timing is unconstrained in both for limit 6. DINO is unchanged: no published Verilog (Chisel only; owner's decision).

Fourth pass (night of 31 October). Two results since the tables below were made:

• CVA6 alu, antenna re-run. The build's automatic antenna retry was measured on it: BLD-20261031-0124 failed sign-off on 5 antenna violations only, the lab rebuilt once with the strongest antenna repair (BLD-20261031-0125, 58 min) and sign-off still failed on 4 antenna violations. Equivalence stays PROVEN-full, CDC and power-on pass, lint still fails on 26 warnings and DFT still gives no coverage. The block needs a design-level fix (diode insertion or a larger die with more routing room) that the lab does not make for you.
• CORE-ET minion_tlb on all four processes, built from the Slang elaboration with its module tree kept: SKY130 BLD-20261031-0162, GF180MCU BLD-20261031-0185 (600 µm die), IHP SG13G2 BLD-20261031-0186 and ASAP7 BLD-20261031-0187 all PASSED (DRC, LVS and antenna clean on the three sign-off processes; ASAP7 is the learning flow without sign-off). Its equivalence is REFUTED-unsupported on every process for the same reason as before: the design clocks flip-flops on both edges.

Families#

RISC-V core (1 design)#

DINO (3 designs): no Verilog source#

SingleCycleCPU, PipelinedCPU, PipelinedDualIssueCPU (LiveHD: 4.7k, 5.1k and 10.7k nodes).

CVA6 (46 blocks) and CORE-ET (122 blocks)#

First block of each family measured below; the runner goes on through the lists night after night (one build at a time, never while a student build is queued).

Rows recorded by the runner (newest row per design; builds through the Slang reader are marked)#

<!-- generated by bench/bench_livehd.py --table on 2026-10-31 13:16Z -->

CVA6 (1 designs)#

CORE-ET (1 designs)#

How the page is refreshed#

sudo python3 -I bench/bench_livehd.py adds rows to bench/livehd-results.jsonl; --table writes the family tables above; the page is rewritten at the end of each benchmark night and the qualification envelope takes its largest clean build from it. Pace: DINO and CVA6 first, then CORE-ET across the following nights (about 20 minutes per build).