The ASIC flow

Physical design turns a list of gates into shapes that can be manufactured. In the lab it is the Build the chip stage, run by OpenLane. The bar on the build card follows these seven phases.

1. Prepare#

The build checks the code and synthesizes it again with its own settings, so the gates match the build's clock and library.

2. Floorplan#

The tool sets the size of the die, lays out the rows where cells will sit, places the input and output pins around the edge, and builds the power grid: the metal stripes that bring supply and ground to every cell.

3. Placement#

Every cell gets a position in a row. Cells that talk to each other are pulled close together, because short wires are faster and easier to route.

4. Clock tree#

The clock must reach every flip-flop at nearly the same moment. The tool builds a tree of buffers to deliver it evenly. The small difference that remains is called skew.

5. Routing#

The tool draws the metal wires that join the cells, on several layers stacked above them. First it plans roughly where each wire goes, then it draws the exact shapes.

6. Timing#

With the real wires known, the tool measures how long every path takes and compares it with the clock. See Timing explained.

7. Sign-off#

Final checks that the layout can be made and matches the design:

• Design-rule check (DRC). Every shape obeys the process's rules for width and spacing.
• Layout versus schematic (LVS). The drawn layout is electrically the same as the netlist.
• Antenna check. No long wire can damage a transistor during manufacturing.

When all of these pass, the build writes the layout file.

When a build fails#

The first step that failed is the place to look. The build card names it.