Clock tree synthesis

Delivering the clock to every flip-flop at nearly the same moment.

StudentEngineer 1 min read · Updated 2026-10-05

        On this page
        What it buildsThe two numbersAfter the tree is builtWhy you must not build your ownIn this lab
      

In your RTL the clock is one wire that reaches everything at once. On silicon that is impossible: one pin cannot drive hundreds of flip-flops, and a wire across the die takes time. Clock tree synthesis builds the real thing.

What it builds#

A tree of buffers. The clock pin drives a few buffers, each drives a few more, and the last ones drive the flip-flops. The tool balances the branches so the clock takes nearly the same time down every path.

A clock tree, as a diagram.

The two numbers#

Term	Meaning
Insertion delay	How long the clock takes from the pin to a flip-flop
Skew	The difference in arrival time between two flip-flops

Skew is the one that matters for correctness. If the clock reaches the receiving flip-flop late, the sending one has more time, which helps setup and hurts hold. Too much skew causes hold violations.

After the tree is built#

Timing is checked again with the real clock delays, and the tool repairs what the tree disturbed, mostly hold problems, by adding small delay cells.

Why you must not build your own#

Gating or dividing the clock with ordinary logic in the RTL creates a second clock the tool has not balanced. The lab's RTL coding standard forbids it. Use an enable on the flip-flop.

In this lab#

The Clock tree phase of the build card. nelix ai cts asks the clock-tree specialist to read the result of a finished build.

Timing analysisSetup, hold, slack and corners in plain words, and what to do when timing is not met.
Clocks and resetsWhat the clock and the reset do, the reset style this lab uses, and the mistakes to avoid.