Manufacturing boundary
One place that says what the lab does on the way to a real chip, at what level, and what it leaves to you, the shuttle or the foundry.
The lab takes a design from RTL to a checked layout and a submission package. Making, testing and packaging real chips happens outside the lab. This page draws that line in one place. If another page seems to say something different, this page is the one that holds.
Each row below is one of three levels:
- Done in the lab: a measured result from the build or a check.
- Teaching level: the check runs and its result is real, but it is not what a production test or sign-off flow does.
- Not offered: the lab does none of it.
What the lab does#
| Step | Level | What the lab does | What it does not do |
|---|---|---|---|
| Layout checks (DRC, LVS, antenna) | Done in the lab | Runs the open kit's decks in the build. See Qualification envelope for each deck's class | Foundry sign-off decks; the shuttle's own precheck; density and fill |
| Timing | Done in the lab | Static timing at each process's corners (9 on SKY130 and GF180MCU, 3 on IHP SG13G2, 1 on ASAP7) | Timing on silicon, or across temperature beyond the corners |
| Submission package | Done in the lab | The Tapeout page builds a package (GDS, netlists, LEF, DEF, SDC, SPEF, reports, waivers). A build that misses timing or skips a required check is blocked unless there is a waiver. See Tapeout gates and waivers | It does not submit for you. You submit to the shuttle |
| Design for test (DFT) | Teaching level | Stuck-at ATPG with Fault 0.9.4 on the gate-level netlist of a passed build, with a full-scan model and a scan-inserted netlist kept as a file. It passes at 90 % coverage, which is a teaching threshold. Supported on SKY130, GF180MCU and IHP SG13G2; not on ASAP7. See Clock crossings, scan test and virtual bring-up | A normal build has no scan chain in its layout; V&V → DFT: scan chain built into the chip builds one into a separate -scan project (SKY130, GF180MCU, IHP SG13G2), checks it is in the layout, and runs the ATPG again on the built netlist. Transition (at-speed) faults are graded at logic level only (launch-on-capture pairs, no path delays, no at-speed ATPG); no bridging faults, no deterministic full ATPG, patterns export as STIL (checked by simulation, 0 mismatches) but are not qualified on a tester (no WGL), no memory test (BIST) |
| Bring-up | Teaching level | A virtual power-on: a scripted simulation of reset, register access and your own sequence on the gate-level netlist (on ASAP7, the RTL) | Testing real chips that come back from the fab |
| Clock and reset crossings | Teaching level | A structural crossing check of your RTL | Constraint-aware CDC sign-off |
| Power and IR drop | Teaching level | A vectorless power estimate and static IR drop; power from your own tests; DC electromigration of the power grid against the kit's limits (SKY130, GF180MCU, IHP SG13G2). See Seeds, proof limits, equivalence and the SystemVerilog subset | Dynamic (time-varying) IR drop and electromigration of signal wires: not available in open source |
| Test structures | Not offered | Process monitors, test keys, scribe-line structures | |
| Pads, padframe, ESD | Not offered | Designs end in plain pins on the die edge | Pad ring, ESD protection, a seal ring (IHP requires one) |
| Packaging and boards | Not offered | Package choice, bonding, a test board | |
| Reliability and production test | Not offered | Burn-in, ageing, qualification, wafer sort, final test | |
| IP and licence checks | Not offered | The open-source notices list the licences of the kits and tools; downloaded layouts contain the kit's own cell layouts | Checking your own design or third-party IP for patents or licences |
What this means for you#
- A clean build and a package from the Tapeout page are the start of a submission, not the end. The shuttle's precheck decides whether it accepts the design.
- "DFT pass" means the netlist is testable at teaching level. It does not mean the chip has a working scan chain; only a
-scanproject built by DFT: scan chain built into the chip has one in its layout. - "Bring-up pass" means the simulated chip starts up as your sequence expects. A real chip can still fail.
- Nothing the lab shows is a silicon or yield guarantee. The open kits are preview kits: SkyWater and GlobalFoundries call theirs experimental, and IHP calls SG13G2 a preview.
Where to go next: Get your chip made lists the four shuttle routes and what each one needs.
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