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Tapeout gates and waivers

Which build the Tapeout page uses, which readiness checks block a submission package, how a waiver is recorded and where it travels, and what the lab really checks per process.

StudentEngineer 6 min read · Updated 2026-10-30

On this page 1. Only a build that meets timing is used2. Required checks block the package3. Waivers4. What the lab checks for each processWhere this is not enforcedSecond-person waivers, more readiness checks and package checksAsk Nelix AgentClass projects and your own projects

The project's Tapeout page (/app/projects/<project>/tapeout) turns a passed build into a submission package for a shuttle. Three rules make sure the package only says what was measured.

1. Only a build that meets timing is used#

"Passed" on a chip build means the layout checks (DRC, LVS, antenna) were clean. It does not mean the chip is fast enough: a build can be Built, timing not met (see Build results).

The Tapeout page therefore takes the newest passed build whose own report also meets timing: setup and hold slack both at or above zero, read from that build's report. Under the readiness list it says which build it uses, and for every newer passed build it skipped, why:

If no passed build meets timing, the page says No build can be taped out yet with the same reason, and no package can be made. Fix the timing (a slower clock, fewer logic levels, pipelining) and build again.

2. Required checks block the package#

Every readiness row is one of three kinds:

KindExamplesWhile it fails or did not run
Requiredthe build passed, Magic/KLayout DRC, routing DRC, LVS, antenna, timing at every corner, electrical rule checks, IR drop, die fits the shuttle, pins fit, clock within the shuttle's limit, GDS stored, the GF180 KLayout deck (until you run it)Blocks the package and the review unless a waiver is recorded
You do this yourselfthe shuttle's own precheck, the Tiny Tapeout tt_um_ wrapper, the wafer.space pad ring, the Caravel harness, IHP's seal ring and filler cells, everything listed under "Not checked by the lab"Never blocks; listed in the package README under You must do this yourself
Does not applychecks a process has no tool for (ASAP7's DRC/LVS/antenna)Shown as "does not apply", with the honest reason

When a required check is open, the page's status line says Tapeout package blocked: N checks fail or did not run and names them. Download a draft package and Make the package and ask for review answer with the same sentence instead of a file.

3. Waivers#

A waiver records that a named check is knowingly skipped. It never makes the check pass; it makes the decision visible and traceable.

  • Next to each blocking row there is Record a waiver. The reason is required (at least 10 characters: why the check may be skipped, and who decided). An empty or too-short reason is refused.
  • The lab records the check, the reason, who recorded it (your name or e-mail and account id) and the date. The owner of a project may always record a waiver; it is then marked self-approved so a reviewer or a shuttle can see that no second person approved it.
  • Waivers are listed in the Waivers section of the page, each with a Remove button. Removing a waiver makes the check block again.
  • Waivers travel with the design: in the submission package readiness.json carries a waiver entry on each waived row, waivers.json lists them all, and the README has a Waivers section; the reproducibility bundle also gets waivers.json and a README line.

A waiver is not a substitute for a reviewer. The Tapeout review by your teacher or mentor still happens after the Sign-off gate, and the reviewer sees every waiver in the package.

4. What the lab checks for each process#

The Tapeout page, the sign-off checklist on every chip report and each process page show What the lab checks for <process>: which DRC rule decks run, whether LVS and the antenna check run, that density and fill rules are not checked (the shuttle adds fill), the timing corners (and that the flow's own violation check looks at the typical corners only, while the lab's checklist looks at every corner), the extraction (parasitics) corners, and that IR drop is static only (average current, no dynamic or transient analysis) and power is a vectorless estimate (the timing tool's default switching activity, no simulation activity).

In short:

ProcessDRC decksLVSAntennaTiming cornersParasitics
SKY130Magic + KLayout, in the buildNetgenyes9 (tt/ss/ff × nom/min/max wiring)nom, min, max
GF180MCUMagic in the build; GlobalFoundries' KLayout deck on request (density and antenna rules of that deck excluded)Netgenyes9nom, min, max
IHP SG13G2Magic + KLayout, in the buildNetgen (no KLayout LVS)yes3, all at nominal wiringnominal only
ASAP7 (learning)route DRC onlynot runnot runthe flow's default (fast) corner onlynone kept

DFT (stuck-at ATPG on the netlist) is teaching level on SKY130, GF180MCU and IHP SG13G2 and not supported on ASAP7. A normal build has no scan chain; V&V → DFT: scan chain built into the chip builds one into a separate -scan project on SKY130, GF180MCU and IHP SG13G2 and checks it in the layout (on 30 October 2026: 57 of 57 scan flip-flops, DRC/LVS/antenna clean, ATPG 97.8 / 97.0 / 96.8 %). What the lab does and does not do on the way to a real chip is on Manufacturing boundary.

Every "not run", "not checked" and "nominal only" above is also written into the checklist rows themselves, so a report never shows a green tick for something that was not measured.

Where this is not enforced#

The orchestrator's own pass rule is unchanged: a build is still PASSED when its layout checks are clean, and the amber Built, timing not met label stays as it was. The gate lives on the Tapeout page only. Reviewer-approved waivers (recorded by the reviewer from the shared page) are not available yet: today every waiver is recorded by the project's owner and marked self-approved.

Second-person waivers, more readiness checks and package checks#

On for every account since 30 October 2026. It adds:

  • Record a waiver sends the waiver to a reviewer of the project instead of recording it at once. It counts only after the reviewer approves it on their shared page (Waivers to review); the reviewer's name is recorded with it. A waiver approved by its own author (the older self-approved kind) no longer unblocks a check: the row stays blocked and says why. The page shows the waivers still waiting for a reviewer.
  • Three more required readiness checks: Timing analysed at every expected corner (a missing corner blocks: "timing not analysed at <corner>"), Coverage closure (against the design class declared on the V&V tab; a metric below its threshold blocks unless a second person waived it), and Evidence unchanged since it was recorded (blocks when a report a V&V row rests on changed after the lab hashed it).
  • The package also contains vv-evidence.json (the V&V rows with the sha256 of every report and the RTL fingerprint), and waivers.json lists the second-person waivers too.
  • Check next to a stored package unzips it and re-hashes every file against its MANIFEST.json, and compares the zip with the sha256 recorded when it was stored (sudo nelix-vv-gates verify-package <user> <project> <PKG-id> does the same on the server).

Ask Nelix Agent#

Ask Nelix Agent on the Tapeout page opens Design Chat with the gate's verdict already in the question (what blocks the tapeout and what to fix first; or, when the design is ready, what the package proves and what is still a risk), and the Ask Nelix Agent next to Record a waiver asks whether a waiver is appropriate for that check. The Agent explains and recommends; it never records a waiver and never changes a check's result.

Class projects and your own projects#

The second-person rule and the coverage-closure block apply to class projects only: a project you submitted to an assignment. There, a waiver counts only after a reviewer of the project (such as your teacher) approves it, and coverage closure for the declared design class must be met or waived before a tapeout package. On your own projects you keep full authority: a waiver you record counts at once with your name as the approver, coverage closure is shown as advice, and no design class is required.

Related

  • Get your chip madeThe four shuttle routes that take a design from this lab to real silicon, which ones fit your process, and how to prepare a submission package.
  • Build results: Passed, timing not met, FailedWhat the green, amber and red labels on a chip build mean.
  • Final artefacts and handoffWhat a finished build gives you, and the gap between a checked layout and a design ready to manufacture.
  • Supported processesThe four processes you can build for, what each is for, and which can become a real chip.
  • Manufacturing boundaryOne place that says what the lab does on the way to a real chip, at what level, and what it leaves to you, the shuttle or the foundry.

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