Qualification envelope

This page states what the lab has actually shown on each process. Every number on it comes from a stored build report or a stored release-gate record, and the record's id is given next to it. A design inside this envelope is one the lab has shown it can build and check. A design outside it may still work, but the lab has not shown that yet.

The figures below were taken on 30 October 2026. They come from the stored build reports of the lab's own test and admin accounts, never from a customer's design, and from the release-gate records of 29 October 2026. The page is refreshed after each release-gate run.

Largest clean design per process#

"Clean" means all of the following:

• the build PASSED;
• setup and hold slack were zero or positive at every corner the build checked;
• DRC, LVS and antenna all passed.

ASAP7 has no DRC, LVS or antenna check, so for ASAP7 clean means route DRC was 0.

Since this table was taken (31 October 2026): the largest signed-off SKY130 build is BLD-20261031-0002, the open-source PicoRV32 CPU on the lab's own test account: 7,488 logic cells (23,626 placed cells with its antenna diodes and taps), 550.5 × 550.5 µm, 24 ns, worst setup / hold slack +7.08 / +0.28 ns, DRC, LVS and antenna clean, 23 minutes. It needed the strongest antenna repair setting (Build settings) after four builds with 1 to 4 antenna violations each; the full comparison with OpenLane's published result for the same design is in the lab's benchmark report. The table is refreshed at the next release gate.

The cell counts are the flow's own count of standard cells, so they include tap and fill cells where the flow reports them.

Read this as the qualified size range: from a few dozen cells up to about 2,000 cells on SKY130, 2,500 on GF180MCU and 1,000 on IHP SG13G2, with one clock. Larger designs do build in the lab. The lab has simply not yet shown one clean on a stored, repeatable record.

Tools, versions and limits#

Lint uses Verilator 5.044 in the image nelix-eda-coverage:1. Simulation uses cocotb 2.1.0 and Icarus 12.0 in nelix-eda-worker:3d; SystemVerilog testbenches use Verilator 5.044 with z3, and UVM testbenches Verilator 5.052 with Accellera UVM 2017-1.0 (image nelix-uvm:1). The full image digests are kept in each gate record.

Every process has the same limits:

• one chip build may use up to 60 minutes, 3 GB of memory and 1.75 CPUs;
• Simulate may use 5 minutes and 1 GB, Synthesize 10 minutes and 1.5 GB (see Compute limits);
• digital standard cells only, with one clock;
• no pads or padframe;
• memory only in flip-flops or in the kit's own SRAM blocks.

Class of each rule deck#

The classes mean:

• Open-kit deck: the rule deck published with the open kit. It runs inside the lab's build, and a seeded fault proved that it catches that fault.
• Educational: the check runs, but it is partial, it runs only on request, or it is a teaching-level method.
• Not available: the lab has no tool for that check on that process.

None of these is foundry sign-off. The foundry and each shuttle use their own released decks and their own precheck.

Release gate on 30 October 2026#

Record 20261030-155141, seven references per process (clean, timing-fail, drc-spacing, lvs-short, lint-fail, sim-fail and the new antenna-fail): 25 PASS, 3 not applicable (ASAP7 has no DRC, LVS or antenna), 0 FAIL. SKY130, GF180MCU and IHP SG13G2: 7 of 7. ASAP7: 4 of 4 applicable. The gate now reruns every week (first run 1 November 2026).

The first full gate, 29 October 2026#

Details: Reference checks and release gate.

Claims the lab does not make#

• No silicon, yield or performance guarantee. All numbers are post-layout tool results.
• No foundry sign-off and no shuttle precheck. A clean build here can still be refused by a shuttle.
• The kits are open preview kits. SkyWater and GlobalFoundries call their open kits an experimental preview, not intended for production. IHP calls SG13G2 a preview. Rules and cells may change between kit releases.
• ASAP7 cannot be manufactured. It is a predictive kit for learning.
• No density or fill check. The shuttle adds fill.
• IHP SG13G2: no seal ring or filler cells are added, and there is no KLayout LVS.
• Timing is only checked at the corners listed above. Power is a vectorless estimate (or measured from your own tests), and IR drop is static only. Electromigration is checked for the power grid only (DC, against the kit's LEF limits).
• DFT is teaching level: stuck-at ATPG, a scan chain that can be built into a separate -scan chip, and transition faults graded at logic level only (no path delays, no deterministic at-speed ATPG). See Manufacturing boundary.
• No analog or mixed-signal design in the digital flow. The Analog Lab is described separately.
• No pads, ESD protection, packaging, reliability or ageing analysis, and no electromigration check of signal wires.