Floorplanning and power planning

Setting the size of the die, where cells may go, and how power reaches them.

StudentEngineer 2 min read · Updated 2026-10-05

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        What is decidedPower planningUtilisationIn this labCommon failures
      

Floorplanning is the first physical step. Before any cell is placed, the tool decides the shape of the chip and prepares the ground.

What is decided#

The die. The rectangle of silicon. In this lab its size is given by DIE_AREA in openlane/config.json.
The core. The area inside the die where cells may be placed, with a margin around it.
The rows. Standard cells all have the same height, so the core is ruled into rows for them to sit in.
The pins. Each input and output of top gets a position on the edge of the die.

A floorplan, as a diagram. The die is the whole rectangle; cells may only be placed in the rows of the core.

Power planning#

Every cell needs supply and ground. The tool builds a power grid: wide metal stripes across the die, joined down to rails that run along every row. Cells are powered simply by sitting in a row.

A grid that is too sparse lets the voltage sag at cells far from the supply. A grid that is too dense takes routing space from signals.

Utilisation#

Utilisation is the fraction of the core that cells occupy. It is the number to watch.

Utilisation	What happens
Very low	The build succeeds, with most of the die empty
Moderate	Room to place and route comfortably
Too high	Placement or routing fails: there is nowhere to put the wires

The starters ask placement to target a density of 50 percent (PL_TARGET_DENSITY_PCT).

In this lab#

The build card's Floorplan phase covers these steps. When a build fails because the design does not fit, the card says so, and the lab may offer a larger die for you to accept.

Common failures#

Symptom	Cause	What to do
The design does not fit	The die is too small for the logic	Accept the offered die, or enlarge `DIE_AREA`
A power-grid error on a very small die	The die is too small for the grid's stripes	Use a larger die. The Blank starter builds at 100 by 100 micrometres

The ASIC flowWhat happens inside Build the chip, phase by phase, from an empty die to a checked layout.
Configuration filesThe actual fields of openlane/config.json, config/project.toml and constraints/clock.sdc, with the values a starter ships with.