OpenLane and OpenROAD
The flow that turns RTL into a layout, and the tools it runs along the way.
On this page
In this labWhat OpenLane runsWhere a build's files goStep names in the logChecks that stop a buildWhat you controlOpenLane is an open-source flow: a program that runs a long series of tools in the right order to take RTL to a layout. OpenROAD is the tool inside it that does the physical design.
In this lab#
| Flow and version | OpenLane 2.3.10 on SKY130 and GF180MCU; LibreLane 3.0.14 (OpenLane's successor) on IHP SG13G2; the OpenROAD flow scripts 26Q3-705-gecb3cfdeb on ASAP7 |
| Used by | The Build the chip stage, nelix build |
| Settings | openlane/config.json in your project |
| Process | The one in config/project.toml: sky130A, gf180mcuD, ihp-sg13g2 or asap7. Tool versions per process: Toolchain overview |
What OpenLane runs#
On SKY130, GF180MCU and IHP SG13G2, a build is dozens of named steps. They group into the phases shown on the build card.
| Phase | Tool | Work |
|---|---|---|
| Prepare | Verilator, Yosys | Lint the code, synthesize onto the process's standard cells |
| Floorplan | OpenROAD | Die, rows, pins, power grid |
| Placement | OpenROAD | Global and detailed placement, design repair |
| Clock tree | OpenROAD | Build and balance the clock tree |
| Routing | OpenROAD | Global and detailed routing, antenna repair |
| Timing | OpenROAD | Extract the wires, analyse timing at each corner |
| Sign-off | Magic, KLayout, Netgen | Write the layout, DRC, LVS, final checks (on GF180MCU, OpenLane skips the KLayout DRC) |
On ASAP7 (learning only) the OpenROAD flow scripts run synthesis, then ORFS.Floorplan, ORFS.Place, ORFS.CTS, ORFS.Route and ORFS.Finish. There is no sign-off DRC or LVS, and times are in picoseconds (ps).
Where a build's files go#
Each build writes its working files to openlane/runs/<run id>/ in your project, one numbered folder per step. The final results are in that run's final/ folder. These files are large; the lab keeps the important ones and shows them through the report and the viewers.
Step names in the log#
The log names each step as it starts, in the form Tool.Step, such as OpenROAD.GlobalPlacement or Magic.DRC. The last step named before a failure is where to look. The stage card reads this for you.
Checks that stop a build#
OpenLane ends with checks that fail the build if a problem remains: unmapped cells, setup or hold violations, design-rule violations, an LVS mismatch, disconnected pins. The build card and the chip report name which one.
What you control#
The settings in openlane/config.json. The starters set the clock, the die and the antenna protection. See Configuration files. The flow has many more settings; the lab's starters leave them at their defaults.
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