Clock and constraint problems
The build cannot find the clock, or the clock settings disagree with each other.
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The build cannot find the clockThe clock is written in three placesThe period is in nanosecondsconfig.json will not loadMore than one clockTiming is met with an unrealistic clockThe build cannot find the clock#
CLOCK_PORT in openlane/config.json must name an input of top.
| Situation | Fix |
|---|---|
| You renamed the clock in the RTL | Change CLOCK_PORT to match, and get_ports in constraints/clock.sdc |
| The design has no clock | The lab's starters and settings assume a clocked design. Register the outputs, as the Blank starter does |
The clock is written in three places#
| File | Field |
|---|---|
openlane/config.json | CLOCK_PERIOD |
constraints/clock.sdc | create_clock -period |
config/project.toml | [clock] period_ns |
The build uses the first. If you change the period, change all three, so the project does not describe itself two ways.
The period is in nanoseconds#
CLOCK_PERIOD: 10 is 10 ns, which is 100 MHz. A common slip is to enter a frequency.
| You want | Enter |
|---|---|
| 50 MHz | 20 |
| 100 MHz | 10 |
| 200 MHz | 5 |
config.json will not load#
It is JSON, and JSON is strict.
| Mistake | Example |
|---|---|
| A comma after the last item | "CLOCK_PERIOD": 10, followed by } |
| A missing comma between items | Two lines with nothing between them |
| Single quotes | 'clk' must be "clk" |
| A comment | JSON has none |
If in doubt, compare with a fresh starter: nelix new scratch --template blank.
More than one clock#
The lab's flow supports one clock. A design with a second clock, or one that makes its own by dividing or gating, is outside it. Use one clock and enables. See Clocks and resets.
Timing is met with an unrealistic clock#
A very long period makes anything pass. That is not a result. Set the period from what the design is for.
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