Timing violations
The build finished and reports that timing was not met.
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First, which kindSetup violationsHold violationsOnly one corner failsGet the evidence read for youTry a fix as an experimentWhat not to doThe build card shows Timing not met. The layout exists, and at the clock you asked for it would not work reliably.
First, which kind#
The chip report gives the worst margin, or slack, for setup and for hold, at each corner.
| Negative slack on | Means |
|---|---|
| Setup | A path is too slow for the clock |
| Hold | A path is too fast |
Setup violations#
The usual case. A chain of logic between two flip-flops takes longer than the period.
| Fix | Cost |
|---|---|
| Put a register in the middle of the long path (pipelining) | One more clock of latency. The specification must allow it, and the test must change |
| Register the inputs before using them | The same |
| Narrow the arithmetic, if the specification allows | Range |
| Lengthen the clock period | Speed. Honest only if the target was wrong, and you say so in the specification |
The MAC-8 starter is the worked example: at 10 ns it missed setup at the slow corner by about 2 ns, because a multiply and an add shared one clock. Its specification records the choice made and the alternative.
Hold violations#
The tools try to repair these by adding delay. If some remain, they need a closer look. Slowing the clock does not help: hold does not depend on the period.
Only one corner fails#
That is still a failure. The slow corner is a hot chip at low voltage, and real chips get hot. See Process corners.
Get the evidence read for you#
nelix timing
nelix explain-timing
nelix ai timingThe timing specialist names the path that sets the limit, citing the build's own measurements, and proposes fixes from an allowed list.
Try a fix as an experiment#
nelix optimize proposeA proposed change is built in a separate copy and compared with the original before you decide. See Build specialists and optimisation.
What not to do#
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