DRC and LVS failures
The layout was written and a final check reports violations.
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Design-rule violationsAntenna violationsAn LVS mismatchAn XOR differenceThe build timed out in a checkAsk a specialistRemember what passing meansThese appear in the Sign-off phase, after routing. The chip report shows which check failed and how many violations it found.
Design-rule violations#
A shape in the layout breaks one of the process's rules. You did not draw the shape; the router did, usually because it ran out of room.
| Do | Why |
|---|---|
| Check whether routing reported congestion | A crowded region is the usual cause |
| Enlarge the die, or lower the placement density | More room lets the router draw legal shapes |
| Build again | The result is the only proof |
Antenna violations#
A long wire could damage a transistor during manufacturing. The starters switch antenna repair on, so these are normally fixed by the build. If some remain, more room usually helps.
An LVS mismatch#
The layout does not match the netlist. In an automated flow this is rare, and it is not usually something in your RTL.
| Cause | Sign |
|---|---|
| A short or an open left by routing | Routing violations were also reported |
| A build cut short | The run timed out during the checks |
Run the build again. If the mismatch repeats with clean routing, report it through Feedback with the run id.
An XOR difference#
The two layout tools wrote layouts that differ. Run the build again. If it repeats, report it with the run id.
The build timed out in a check#
The layout may be finished and only the check cut short. The card says so. Running Build the chip again often completes.
Ask a specialist#
nelix ai drc
nelix ai lvs
nelix ai antennaEach reads the measured result of your latest build and says what it found.
Remember what passing means#
A clean result here is a clean result against the open sky130 kit. It is not acceptance by a foundry. See Final artefacts and handoff.
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