NELIX Silicon Lab Docs Launch Silicon Lab Launch Silicon Lab

DRC and LVS failures

The layout was written and a final check reports violations.

Engineer 1 min read · Updated 2026-10-05

On this page Design-rule violationsAntenna violationsAn LVS mismatchAn XOR differenceThe build timed out in a checkAsk a specialistRemember what passing means

These appear in the Sign-off phase, after routing. The chip report shows which check failed and how many violations it found.

Design-rule violations#

A shape in the layout breaks one of the process's rules. You did not draw the shape; the router did, usually because it ran out of room.

DoWhy
Check whether routing reported congestionA crowded region is the usual cause
Enlarge the die, or lower the placement densityMore room lets the router draw legal shapes
Build againThe result is the only proof

Antenna violations#

A long wire could damage a transistor during manufacturing. The starters switch antenna repair on, so these are normally fixed by the build. If some remain, more room usually helps.

An LVS mismatch#

The layout does not match the netlist. In an automated flow this is rare, and it is not usually something in your RTL.

CauseSign
A short or an open left by routingRouting violations were also reported
A build cut shortThe run timed out during the checks

Run the build again. If the mismatch repeats with clean routing, report it through Feedback with the run id.

An XOR difference#

The two layout tools wrote layouts that differ. Run the build again. If it repeats, report it with the run id.

The build timed out in a check#

The layout may be finished and only the check cut short. The card says so. Running Build the chip again often completes.

Ask a specialist#

sh
nelix ai drc
nelix ai lvs
nelix ai antenna

Each reads the measured result of your latest build and says what it found.

Remember what passing means#

A clean result here is a clean result against the open sky130 kit. It is not acceptance by a foundry. See Final artefacts and handoff.

Related

  • DRC and LVSThe two checks at the end of the build: can it be made, and is it the design you asked for?
  • Design rulesThe limits a factory places on shapes, why they exist, and how they are checked.

Something unclear or missing? Send feedbackSign in and use Feedback to tell us.