Liberty, LEF, GDS and technology files

The file formats that carry a design and a process through the flow, and what each one holds.

Engineer 1 min read · Updated 2026-10-05

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Each tool in the flow reads and writes particular formats. Knowing what each one holds tells you where to look when something goes wrong.

Formats that describe the process and its cells#

Format	Holds	Read by
Liberty (`.lib`)	For each standard cell: its function, its delay under different loads, its power. One file per corner	Synthesis and timing analysis
LEF	The physical outline of each cell: its size, where its pins are, where routing is blocked. Also the routing layers and their rules	Placement and routing
Technology files	Layers, colours and rules in each tool's own format	The layout and checking tools
Rule decks	The checks to run for DRC and LVS	The checking tools

Format	Holds	Written by
Verilog netlist (`.v`)	The design as gates and the connections between them	Synthesis
SDC	Timing constraints: the clock, input and output timing	You
DEF	The design during physical design: where each cell is placed and how each wire is routed	Placement and routing
SPEF	The resistance and capacitance of the routed wires	Extraction, after routing
GDS	The finished layout: every shape on every layer	The end of the build

File	Where you meet it
`constraints/clock.sdc`	In your project. The clock constraint
`reports/top_synth.v`, `reports/top_gates.v`	Netlists from the Synthesize stage
The GDS	The layout the build writes. `nelix layout` opens it
Liberty, LEF, technology files	Part of the process kit on the server. You do not edit them

nelix artifacts lists the files kept for a build.

What a PDK containsThe files a factory provides so that design tools can target its process.
Artefacts and reportsThe files each stage produces, their formats, and how to open them.

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