Generate a testbench

The Testbench tab on a project's page writes a test for your design. It works on every project, Verilog, VHDL or both: the lab reads every design file the Makefile names and finds the top level.

The test is written the way your project is tested: a Python (cocotb) test, a Verilog testbench, a VHDL testbench, or a C++ test built with Verilator.

Generate one#

1. Open the project from Projects and choose the Testbench tab.
2. Optionally, describe what the design should do. The more you say, the better the test.
3. Choose Generate.

What happens#

The page shows three steps, each turning green as it finishes.

Read the result#

• Passes on your RTL. The test and your design agree.
• Fails on your RTL. Either the design has a bug, or the test expects something your design was never meant to do. Read what the test assumed.
• Could not be run. The test or the design did not compile. The message says which.

Under the result, the page lists what the test checks, what it assumed, and what it does not cover.

Use it#

The test is a proposal until you accept it. Replace my testbench writes it into your project and keeps the old test and Makefile; Put back restores both exactly. Then Simulate runs it like any other test.

Start from a template. If you would rather write the test yourself, this gives a starter test with your design's real ports, in your project's test language. No AI is used.

Make it better#

Write the specification first. A test written from a description of intended behaviour can catch a design that is wrong. A test written only from the code tends to agree with the code. See Write a specification and Verification.