Build results: Passed, timing not met, Failed
What the green, amber and red labels on a chip build mean.
On this page
Fixing "timing not met"Every finished chip build gets one of three labels. It is the same on the Overview, the build card, the sign-off card, the AI Workspace, e-mails and Compare.
| Label | Colour | Means |
|---|---|---|
| Passed | Green | The layout checks are clean and timing is met: the chip is fast enough for its clock |
| Built, timing not met | Amber | The layout is fine, but some path is too slow (or too fast, for hold). The label says by how much, with a link to the Timing tab |
| Failed | Red | The build did not finish, or its layout checks failed |
Only the label is new. Builds run exactly as before, and the tools check exactly the same things.
A build that is Built, timing not met is not ready to make: Home's Recent projects and the Overview's Export / tapeout step say "Built, timing not met" instead of "GDS ready", and Design review's Is it ready to make? answers "Not yet". The layout file can still be downloaded, to look at.
Such a build is never offered for a tapeout package: the project's Tapeout page takes the newest passed build that also meets timing (setup and hold, from the build's own report) and says which newer builds it skipped and why. A package or a tapeout review is also refused while a required readiness check fails or did not run, unless a waiver with a reason is recorded. See Tapeout gates and waivers.
On a build that did not finish, the chip report's Nelix Agent card never says "nothing to fix" for timing: it says not measured, or estimate only when the only timing numbers come from before layout.
Fixing "timing not met"#
Open the Timing tab. The worst path shows where the delay is. Common fixes: a slower clock (a larger clock period in the build settings), fewer logic levels between two flip-flops, or splitting a long calculation over two clock cycles (pipelining).
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