Using the platform

Accounts, projects, the editor, running jobs, reading results, drafting with AI and sharing.

• Accounts and workspacesRequest access, wait for approval, set your password, and sign in.
• Creating projectsCreate a project from a starter, switch between projects, and delete one.
• Editor and terminalA code editor and terminal in your browser, inside your project folders.
• Project specificationsThe file that says what a design must do, the sections the starters use, and how the lab and its agents rely on it.
• SimulateRun the test against your design and read the result.
• Synthesize and build the chipTurn the code into gates, then place and route them into a layout.
• Run all three stagesStart simulate, synthesize and build with one button, and follow the build phase by phase.
• Waveforms, reports and artefactsOpen the waveform, the schematic, the layout and the chip report, and read a run's log.
• When a run failsRead the card, ask Nelix Agent for a diagnosis, and accept a repair only when you agree with it.
• Design ChatThe project chat. Ask about your project, or have Nelix Agent draft a specification, a design and a test.
• Share your chipPublish a page with a picture of your layout, download cards for social media, and get a certificate.
• Plans and allowancesWhere you start (student, engineer, university), the starter credit, the four plans (Student, Professional, University, Enterprise), AI credits and top-ups, and what happens at the limit.
• Language and feedbackChoose the language Nelix Agent answers in, and tell Nelix what to improve.
• Progress marks and comparing runsSee how far every project has got, lay two simulations over each other, and set targets the lab checks for you.
• Cells and transistorsLook closely at your layout, see which standard cells your chip is made of, and open any cell to see its transistors.
• Process LabLearn how a fab makes a chip: ten process modules, two films of a chip being built, the Fab floor, your own wafer, checks, real foundry numbers and a certificate, with the Nelix Agent on every step.
• The AI WorkspaceDesign Chat beside live views of your chip, with click-to-inspect and snapshots you can compare.
• Build results: Passed, timing not met, FailedWhat the green, amber and red labels on a chip build mean.
• NotificationsThe bell, e-mails, and how to choose what you get.
• Classes and assignmentsFor teachers: create a class, share the invite code, set graded assignments. For students: join a class and hand in work.
• VHDL projectsDesign in VHDL: make or import a VHDL project, simulate it in GHDL, synthesize it and build the chip.
• Use your own AI keyUse your own AI provider account instead of Nelix Agent.
• Your data and snapshotsWhat the lab keeps about your work, and for how long.
• AutopilotDescribe a block in plain words; Autopilot writes the spec, the RTL and a test, builds the chip, and shows you the measured result.
• Analog LabSimulate real transistor circuits with SPICE on three open processes, follow the five-step analog flow with the Analog Pro cards (waveforms, sweeps, corners, variables, layouts, reliability), learn analog design from zero, and play with circuits in the Analog Studio.
• Get your chip madeThe four shuttle routes that take a design from this lab to real silicon, which ones fit your process, and how to prepare a submission package.
• Tapeout gates and waiversWhich build the Tapeout page uses, which readiness checks block a submission package, how a waiver is recorded and where it travels, and what the lab really checks per process.
• V&V summary and checksThe project's V&V tab, one row per check (lint, simulation, formal, coverage, synthesis, equivalence, DRC, LVS, antenna, timing, IR drop), what each state means, the Lint and RTL-vs-netlist checks, coverage export and exclusions, and the limits.
• Assertions, functional coverage and test historyCheck your RTL's assertions in simulation, measure which values your tests really reached, see every test's result run by run, open a failed run's waveform at the failure, and read which requirement the last run verified.
• Clock crossings, scan test and virtual bring-upThree deeper checks on the V&V page: clock and reset domain crossings in your RTL, a scan/ATPG fault-coverage run on your gate-level netlist, and a scripted power-on of the chip in simulation.
• Layout markers, PVT sweeps and yield binsWhere each DRC violation sits on your chip, what the LVS report names, which wiring parasitics the timing used, one net's resistance and capacitance, area after synthesis next to area after layout, a frequency-per-corner grid, analog supply and temperature sweeps, and the Process Lab's yield bin maps.
• Seeds, proof limits, equivalence and the SystemVerilog subsetWhich SystemVerilog the lab's simulators run (tested), how a random test's seed is kept and replayed, what a formal check that runs out of time means, how equivalence is checked against the synthesis and the final routed netlist, and what the DFT and power checks measure.