Clocks and resets

The clock#

The clock is a signal that switches between 0 and 1 at a steady rate. Each rising edge is a tick on which every flip-flop updates. Nothing stored changes between ticks.

The period is the time from one rising edge to the next. A 10 ns period is 100 MHz. The starters set it in openlane/config.json and constraints/clock.sdc.

The reset#

At power-up a flip-flop holds an unknown value. Reset forces every flip-flop into a known starting state.

The lab's starters use one style throughout: a reset named rst_n that is active low and asynchronous.

• Active low: reset is in force when the signal is 0. The _n in the name says so.
• Asynchronous: reset takes effect at once, without waiting for a clock edge.

always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) acc <= '0;       // reset, immediately
    else if (en) acc <= acc + product;
end

The or negedge rst_n in the sensitivity list is what makes it asynchronous.

In a test#

A test must apply reset before it checks anything, and release it away from the active clock edge.

dut.rst_n.value = 0
await FallingEdge(dut.clk)
await FallingEdge(dut.clk)
dut.rst_n.value = 1

Mistakes to avoid#

An enable, not a second clock#

To make something happen every fourth cycle, do not divide the clock. Count, and use the count as an enable:

always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)        slow <= '0;
    else if (tick_4th) slow <= slow + 1'b1;
end