Synthesis

How code becomes logic gates, and what to look for in the result.

StudentEngineer 2 min read · Updated 2026-10-05

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        What the tool doesTwo kinds of synthesis in this labReading the resultThe schematicCommon problemsWhat synthesis does not tell you
      

Synthesis translates your RTL into a netlist: a list of logic gates and the wires between them.

What the tool does#

Reads and checks the code.
Elaborates it: works out the real size of every signal and expands parameters and generate blocks.
Optimises the logic: removes what is unused, merges what is repeated.
Maps it onto simple gates: AND, OR, XOR, inverters, multiplexers and flip-flops.

Two kinds of synthesis in this lab#

The Synthesize stage runs Yosys with the script synth.ys in your project. It maps the design onto generic gates, not onto the cells of a manufacturing process. That makes it fast, and a good first look at how big a design is.

The Build the chip stage synthesizes again, this time onto the standard cells of the sky130A process. So the two counts differ. For the MAC-8 starter:

Stage	Result
Synthesize	574 generic gates, 20 of them flip-flops
Build the chip	about 2,200 standard cells, which include buffers, fill and protection cells added during physical design

Reading the result#

The synthesis log, reports/synth.log, ends with a count of each gate used:

text

Number of cells:                574
  $_AND_                        270
  $_DFFE_PN0P_                   20
  $_NOT_                          8
  $_OR_                          96
  $_XOR_                        180

Two numbers matter most:

The number of cells. A rough measure of size.
The number of flip-flops: the lines starting $_DFF. One for each bit of state your design stores. MAC-8 stores a 20-bit accumulator, so it has 20.

If the flip-flop count surprises you, the design is storing something you did not intend, or not storing something you did.

Gate counts reported by the Synthesize stage for four designs: the Blank starter, the counter, the ALU from the tutorial, and MAC-8. A multiplier dominates: MAC-8 is mostly its 8 by 8 multiply.

The stage also writes two netlists: reports/top_synth.v, at block level, and reports/top_gates.v, at gate level.

The schematic#

See the schematic draws the block-level netlist. Use it to check that the tools understood your code. A multiplier should look like a multiplier; a register you expected should be there.

The first guided project, an 8-bit counter, as the synthesis tool draws it: two registers ($adff and $adffe), an adder ($add) that feeds the count back plus one, and a comparison ($eq) with 32 that drives done.

Common problems#

Message	Meaning
A latch was inferred	An `always_comb` block does not assign one of its outputs on every path. Give it a default at the top
Multiple drivers	Two blocks assign the same signal
Module not found	A module name is misspelled, or its file is not listed
A construct is not supported	The code uses a language feature the tool does not accept. See the RTL coding standard

What synthesis does not tell you#

It does not tell you whether the design is correct; that is simulation's job. And it does not tell you the final speed, because the wires have not been drawn yet. That comes from the build.

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