Design flows

From a specification to a checked layout: what each step does, in general and in this lab.

• From specification to layoutThe whole journey in one page: what each step does and what it hands to the next.
• RTL coding standardThe rules this lab's designs follow, and why each one exists.
• Simulation and functional verificationHow to write a test that can actually catch a bug, with cocotb.
• SynthesisHow code becomes logic gates, and what to look for in the result.
• The ASIC flowWhat happens inside Build the chip, phase by phase, from an empty die to a checked layout.
• Floorplanning and power planningSetting the size of the die, where cells may go, and how power reaches them.
• PlacementGiving every cell a position, and why where cells sit decides how fast the chip is.
• Clock tree synthesisDelivering the clock to every flip-flop at nearly the same moment.
• RoutingDrawing the metal wires that join the cells, on several layers, without breaking a rule.
• Timing analysisSetup, hold, slack and corners in plain words, and what to do when timing is not met.
• DRC and LVSThe two checks at the end of the build: can it be made, and is it the design you asked for?
• Final artefacts and handoffWhat a finished build gives you, and the gap between a checked layout and a design ready to manufacture.
• Analog design and sign-offDraw or write an analog circuit with the kit's own devices, set a specification, sweep a size, and sign it off over corners, temperatures and Monte Carlo, with Nelix Agent reviewing the results.
• Manufacturing boundaryOne place that says what the lab does on the way to a real chip, at what level, and what it leaves to you, the shuttle or the foundry.