Layout markers, PVT sweeps and yield bins

These pages are available on every project. Everything on them is read from the reports a build kept; nothing is estimated, and a number the build did not record says so.

Layout checks in detail (on the chip report)#

Open a build's chip report (/app/report/<build>). Before Files there is a new section, Layout checks in detail:

• Violation markers: how many design-rule violations have coordinates, grouped by rule and layer, with a button to the Violations page. A clean build says No DRC markers and shows the counts the build measured (Magic and KLayout). Builds made before 2026-10-29 kept KLayout's per-rule counts but not its marker database: for those the page shows the counts and says the places were not kept.
• LVS: the final verdict line of netgen's report, the mismatch sections it printed (with the net and device names), and a link to the full report.
• Parasitic extraction the timing used: SKY130 and GF180 builds extract three RC corners (min, nom, max); IHP builds nominal RC only (the kit ships one RC corner); ASAP7 builds keep one SPEF file since 2026-10-29, none before. The button Look up one net's R and C opens the net lookup below.
• Area: after synthesis vs after layout: standard cells, cell area (µm²) and core utilisation side by side. After synthesis the netlist is only logic; placement, timing repair, hold fixing and the clock tree add cells, so the layout number is normally larger; the growth is shown as a percentage. An ASAP7 build made before 2026-10-29 says synthesis area: not recorded by this flow.
• Frequency per corner (shmoo): how many timing corners were measured, the slowest one, and a link to the grid.

The Violations page#

The Violations page opens from the buttons See the violations on the chip on the Overview's build step, the Results page, the run page, the top of the chip report and the DRC and LVS rows of the V&V tab; its own bar has Back to the chip report, Open the full netgen report, Download marker database and Ask Nelix Agent.

/app/projects/<project>/builds/<build>/violations lists every DRC violation with its rule, the layer it concerns, its position (x, y in micrometres from the layout's lower-left corner) and its size, from KLayout's marker database and Magic's report. The first time you open it for a build with violations, KLayout draws the whole chip with a red box on each violation (click a box to jump to its row) and a close-up of each of the first 24 violations; on SKY130 the rule's layer is outlined in white in the close-up. GF180MCU and IHP SG13G2 pictures use their kit's own layer colours (the same file as the chip pictures); a layer the file does not list is still drawn, in a default colour. Drawing runs in the lab's render container at the lowest priority and takes about a minute. The GF180 KLayout DRC you can run from the Sign-off checklist feeds the same page.

A build that failed (for example on DRC) keeps no layout in the lab's results store: the page then draws the markers on the layout still in your own run folder for that build (openlane/runs/<build>/final/gds/, read as you, never another build's folder) and says drawn on the layout from your run folder; if that folder was cleaned up, the page says so and lists the coordinates only.

Limits: markers come only from reports the build kept, so a build with neither a stored layout nor a layout in its run folder lists coordinates without pictures; the lab does not re-run DRC here. ASAP7 builds run routing checks only (no sign-off DRC or LVS), so their page says No DRC report was kept.

One net's resistance and capacitance#

/app/projects/<project>/builds/<build>/nets (button Look up one net's R and C on the chip report's Layout checks in detail and on the Violations page) reads the SPEF file the build kept (the file of extracted wire parasitics the timing check used) and shows, for the net you type (bus bits as acc[3]; the box suggests every net name):

• Total capacitance in fF, exactly the file's own total for that net, split into capacitance to ground (the wire itself) and coupling to neighbouring wires, with the largest couplings named;
• Wire resistance in Ω, all resistor segments added, and the number of segments and pins;
• who drives the net (a cell's output pin, or an input pin of the chip) and the resistance from the driver to each load along the wire;
• the same net in the build's other RC corners, and the ten nets with the most capacitance.

Per process: SKY130 and GF180MCU builds have three corners (min, nom, max), IHP SG13G2 the nominal corner only, ASAP7 one file (the learning kit's single RC set; its numbers are predictive, not a real factory's). A build that stopped before extraction, or an ASAP7 build made before 29 October 2026, kept no SPEF file: the page says No parasitics for this build. A name the file does not have says Net not found and lists names that contain what you typed. The capacitance of the cell pins themselves is in the cell library, not in the SPEF (the file says PIN_CAP NONE), so it is not included. Only your own builds can be opened.

Measured on the MAC-8 starter (30 October 2026): SKY130 BLD-20261030-0006 net a[0], nominal corner, 0.921 fF total (0.811 ground + 0.110 coupling), 3 segments, 31.39 Ω (19.91 Ω from the pin to the buffer); the same net at the max corner 0.973 fF and 74.67 Ω. Each number was checked by hand against the lines of the SPEF file.

The shmoo grid#

/app/projects/<project>/builds/<build>/shmoo places each corner the build's timing analysis measured on a supply-voltage × temperature grid and shows the highest clock frequency the design would still meet there: 1 / (clock period − setup slack), the same arithmetic as the Compare page. A SKY130 build normally fills three cells (slow 1.60 V 100 °C, typical 1.80 V 25 °C, fast 1.95 V −40 °C); an IHP build three; a GF180 build three; an ASAP7 build one (its flow runs one corner). Cells the kit has a library for but the build did not check say not measured; voltage/temperature pairs with no library in the kit say no library at this corner in the kit. Nothing is interpolated unless you press Show estimates, and those values are labelled estimated everywhere. The page ends with a plain note on derating: why a chip is sold for its slowest corner, not its typical one.

Analog stress sweeps (Analog Lab)#

On a finished analog run's page, Stress sweeps repeats the exact netlist the run simulated with its supply at 0.9×, 1.0× and 1.1× the nominal value (or a range you choose, 0.5× to 1.5×, up to 13 points), or across a temperature range (−55 to 150 °C). The sweep is one ordinary run through the Analog Lab's queue, sandbox and time limit; ngspice changes the supply source's DC value before each repeat (alter), so your files are not touched. The sweep run's page shows every measurement at every point, the biggest drift from the nominal point, and the limit line: the first point, going down and going up from nominal, where a specification fails. Specifications come from the project's analog/<circuit>.specs.json when it ran with the circuit; otherwise add ?lim=measurement:min:max to the page address. A netlist without a recognisable supply source (a line like VDD vdd 0 1.8) is refused with a plain reason. Process corners and Monte Carlo stay in Sign-off.

Yield bin maps (Process Lab)#

The Fab floor gets a sixth part, Yield analytics (/process-lab/floor/yield). Every probed die lands in a bin: 1 pass, 2 speed fail (works but misses the speed spec), 3 power/leakage fail, 4 functional fail (a killer defect); the outer ring is 7 edge and is not counted in the yield. Functional fails come from the same wafer-map model as Defects and maps (defects per die are Poisson with the chosen signature; each kills with the kill ratio); speed and leakage are simulated per die with a per-wafer offset and a centre-fast trend, and leaky dies tend to be the fast ones. Move the defect density and the specs: at a defect density of 0 almost every probed die is bin 1; at a high density bin 4 dominates and the yield falls. Below the map: yield per bin, the yield trend across wafers and lots (the defect density learns from lot to lot, as in TD to HVM) and a failure Pareto. These are simulated dies for teaching, not data from a real fab, and nothing you do here is stored.

Compare page#

The Compare page (/app/processes/compare) has one more row, Area after synthesis, next to the post-layout area; a build whose flow did not record it shows not measured.

Ask Nelix Agent#

Ask Nelix Agent on the Violations page, the shmoo page, the chip report's Layout checks in detail and an analog stress sweep opens Design Chat with the key facts on that page already in the question (the rule counts and the first marker, the LVS verdict, the measured corners and the slowest one, the sweep's limit line and drift). It explains and recommends; the measured numbers stay as the tools reported them.