Compilation and top-module errors

The design will not compile, or the tools cannot find the module named top.

StudentEngineer 1 min read · Updated 2026-10-05

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        Find the first errorSyntax errorsThe top module cannot be foundUndeclared signalsIt compiles in one stage and not anotherThe test file will not load
      

These errors appear at the very start of a run, before any test executes.

Find the first error#

The first error is the real one. Later errors are usually consequences. Open the run's log on the Runs page, or:

nelix logs TST-20261005-0001

Syntax errors#

text

rtl/top.sv:14: syntax error

Look for	At
A missing `;`	The line before the one named
A `begin` without an `end`, or the reverse	The block containing that line
A missing `endmodule` or `endcase`	The end of the file or the `case`
A stray character from pasting	The first line of the file

The simulator reports the line where it gave up, which is often one after the mistake.

The top module cannot be found#

Message	Cause	Fix
`Module \top not found`, or the simulator cannot find `top`	The module has another name	Name it `top`. The starter's `Makefile`, `synth.ys` and `config.json` all expect that
The same, with the right name	The file is not at `rtl/top.sv`	Put the design back at that path
`Unknown module type: foo`	`top` uses a module that is not defined	Define it in `rtl/top.sv`, or fix the spelling

Undeclared signals#

text

Unable to bind wire/reg/memory 'cnt'

A signal is used and never declared, often a misspelling. Starting the file with ` default_nettype none `` turns every such slip into a clear error at the right line.

It compiles in one stage and not another#

Simulate uses Icarus Verilog; Synthesize uses Yosys 0.33; the build uses Yosys 0.46. A construct one accepts, another may not. Keep to the constructs in the RTL coding standard.

The test file will not load#

Message	Cause
`ModuleNotFoundError`	The test imports something the lab does not allow. Only `cocotb`, `cocotb.clock`, `cocotb.triggers` and `random` are available to a test
`unexpected keyword argument 'units'`	Code written for cocotb 1. Here it is `unit="ns"`
`SyntaxError` or `IndentationError`	A Python mistake in `tb/test_top.py`, at the line named

Icarus VerilogThe simulator behind the Simulate stage: what it does, its version here, and its common messages.
Project structureEvery file in a project, what it is for, and which ones must stay where they are.

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