Creating projects
Create a project from a starter, switch between projects, and delete one.
A project is one design: its code, its test, its build settings and every run you have made of it.
Create a project#
On the Projects page, choose New project. Give it a name, choose the Language (Verilog, VHDL, or Verilog + VHDL), pick a starter design and a Process (SKY130, GF180MCU, IHP SG13G2 or ASAP7; see Supported processes), then choose Create project. A VHDL project starts from an 8-bit counter and its test; a Verilog + VHDL project starts from a Verilog top that uses a VHDL counter. See VHDL projects.
Test with. Choose how the project is tested. The list only offers what the language can use:
| Language | Test choices |
|---|---|
| Verilog | Python (cocotb), Verilog testbench, C++ with Verilator |
| VHDL | VHDL testbench, Python (cocotb) |
| Verilog + VHDL | Python (cocotb), Verilog testbench |
The project starts with a test in that language for the starter's real ports, and Simulate runs it. A Verilog or VHDL testbench passes when it finishes without printing FAIL or ERROR. A C++ test (tb/tb_<top>.cpp) is built with Verilator and passes when the program returns 0 and prints no FAIL or ERROR. The waveform is kept for every choice. Nelix Agent can write a test in any of these languages on the Testbench tab, C++ included.
Memory block (SRAM). This starter uses a ready-made memory block from the process kit instead of thousands of flip-flops. See the in-lab guide Memory blocks (/app/guide/memory).
Analog Lab projects#
An Analog Lab project simulates a transistor circuit with ngspice. Besides the inverter it starts with, its page has two cards:
- Circuit library: current mirror, cascode, common-source amplifier, bandwidth, source follower, differential pair, 5-transistor OTA and two-stage op-amp. Each is added as
analog/<circuit>-<process>.cir. The run page shows the results with their units (gain in dB, phase in degrees, power in watts) and Try changing it boxes for the sizes, within safe ranges; Save these sizes keeps them. - My circuit: write your own SPICE netlist. It starts from a small example for the process, and buttons insert parts and analyses with the right names. Before it saves, the lab checks there is an analysis, the process's models and
.end, and no shell commands or files outside the kit. It then runs in the same sandbox and time limit as the library circuits.
To start from a design that is already on GitHub, choose Import from GitHub on the New project page and paste the address of a public repository. Verilog (.v), SystemVerilog (.sv) and VHDL (.vhd, .vhdl) files are taken; nothing from the repository is run. The address may name a branch, a tag or a commit with a folder (https://github.com/owner/repo/tree/<branch or commit>/<folder>); the import page shows the commit it took. Files kept elsewhere in the repository (since 31 October 2026): when the folder's files import packages or use modules kept elsewhere in the repository, the import asks Slang what is missing and adds the files that define it, up to six rounds, and lists every added file with where it came from and what it defines; nothing is added that Slang did not ask for. Chip builds of the new project then choose the reader automatically: your own files when the flow's reader takes them, the Slang preparation when it does not (see How the lab reads your design under Chip build settings). If the repository has no test, the import adds a placeholder tb/test_top.py that fails on purpose; a test you add to tb/ later (a test_*.py with @cocotb.test, or a Verilog/SystemVerilog or VHDL testbench) is picked up at the next Simulate, and the Testbench page shows which test files Simulate runs.
You can also create a SKY130 project in the Workspace terminal:
nelix new mychip
cd ~/project/mychipA name is letters, numbers, hyphens and underscores, up to 64 characters, starting with a letter or a number. No spaces.
nelix new asks you to choose a starter. Press Enter to take the recommended one.
| Starter | Command | What it is |
|---|---|---|
| MAC-8 (recommended) | nelix new NAME | A signed 8-bit multiply-accumulate unit |
| UART TX | nelix new NAME --template uart-tx | A serial transmitter |
| FIFO | nelix new NAME --template fifo | A first-in, first-out buffer |
| Blank | nelix new NAME --template blank | A minimal design to replace with your own |
nelix new NAME --default skips the menu and uses MAC-8. nelix learn lists guided projects.
After creating a project, go back to Overview and refresh. It appears in the Project menu.
Switch project#
Use the Project menu at the top of the left panel, or the Switch project menu beside the project name on Overview.
Delete a project#
On the Projects page, choose Delete on the project's row, type the project's name to confirm, and choose Delete project.
Deleting moves the project to Recently deleted on the Projects page, with its files, runs, results and Design Chat conversations, and takes down its public share page. For 7 days you can Restore it; after that, or when you choose Delete now, it is deleted for good. Your usage records are always kept.
While a project is in Recently deleted, its files still use your student space. To free the space at once, open Recently deleted (the button above your project list, or the link in the space warning) and choose Delete now.
Several at once. On the Projects page, tick the projects and choose Delete selected: they go to Recently deleted. On Recently deleted, tick projects, or tick the box at the top of the list to select them all, and choose Delete selected, then type delete to confirm: they are deleted for good and their space is free at once. A project with a run in progress is skipped.
If you make a new project with the same name as one you deleted, the new project starts empty: the deleted one stays in Recently deleted under its own name (the old name followed by the date and time it was deleted), so its runs never show up in the new project.
What is in a project#
See Project layout for every file and what it does.
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