FPGA versus ASIC
How the same RTL becomes two very different kinds of hardware.
On this page
What an FPGA isWhat an ASIC isThe flows side by sideWhat carries overWhat does notIn this labBoth start from the same RTL and the same simulation. They part ways at synthesis.
What an FPGA is#
A field-programmable gate array is a manufactured chip full of small configurable logic blocks, called lookup tables, with flip-flops and a programmable web of wires between them. "Building" a design means working out a configuration that makes those blocks and wires behave like your circuit.
What an ASIC is#
An application-specific integrated circuit is manufactured for one design. Its gates are standard cells placed where the design needs them, joined by wires drawn for it.
The flows side by side#
| Step | FPGA | ASIC |
|---|---|---|
| Synthesis maps logic onto | Lookup tables and flip-flops | Standard cells |
| Placement puts logic into | Fixed sites that already exist | Rows on an empty die |
| Routing uses | Wires that already exist, joined by switches | New metal, drawn for the design |
| Clock distribution | A network built into the chip | A tree built for the design |
| Final checks | Timing | Timing, design rules, layout versus schematic |
| Output | A configuration file | A layout |
What carries over#
- The RTL, if it avoids features tied to one target.
- The test. Simulation does not care what the design will become.
- The ideas: clocks, resets, state machines, pipelining, timing.
What does not#
- Memory. An FPGA has block memories built in. An ASIC needs memory macros, or builds storage from flip-flops, as this lab's flow does.
- Reset habits. FPGA flip-flops usually power up in a known state. ASIC flip-flops do not.
- Speed numbers. They are not comparable between the two.
In this lab#
The lab runs the ASIC flow. There is no FPGA flow today. See Choosing FPGA or ASIC.
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