Configuration files

Three files hold a project's settings. The examples below are the files of the Blank starter, unchanged.

openlane/config.json#

The settings the build reads.

{
    "DESIGN_NAME": "top",
    "VERILOG_FILES": [
        "dir::../rtl/top.sv"
    ],
    "CLOCK_PORT": "clk",
    "CLOCK_PERIOD": 10,
    "FP_SIZING": "absolute",
    "DIE_AREA": [0, 0, 100, 100],
    "PL_TARGET_DENSITY_PCT": 50,
    "GRT_REPAIR_ANTENNAS": true,
    "RUN_HEURISTIC_DIODE_INSERTION": true,
    "DIODE_ON_PORTS": "in"
}

Starter values differ by design. Blank uses a 100 by 100 micrometre die at 10 ns. MAC-8 uses a 15 ns clock, for the reason its specification gives.

constraints/clock.sdc#

The clock constraint, in the industry's standard format.

# Clock constraint for this design.
# The ASIC build takes the same clock from openlane/config.json
# (CLOCK_PORT, CLOCK_PERIOD). Keep the two in step if you change one.
create_clock -name clk -period 10.0 [get_ports clk]

If you change the clock period, change it in both files.

The build applies this file itself (PNR_SDC_FILE / SIGNOFF_SDC_FILE) on SKY130, GF180MCU and IHP, after checking that it holds only plain timing constraints; see Timing constraints.

config/project.toml#

A description of the project. The lab's tools read it; you rarely edit it.

[project]
name = "blank"
title = "Blank Project"
kind = "starter"
top = "top"
target = "asic"

[sources]
rtl = ["rtl/top.sv"]

[clock]
port = "clk"
period_ns = 10.0

[reset]
port = "rst_n"
active = "low"
style = "asynchronous"

[verification]
testbench = "tb/test_top.py"
framework = "cocotb"
simulator = "icarus"

[asic]
flow = "openlane"
pdk = "sky130A"
config = "openlane/config.json"
die_area_um = [100, 100]

[docs]
design = "docs/DESIGN.md"

Editing safely#

• config.json is JSON: keep the quotes, commas and brackets exactly.
• After changing the clock or the die, run Build the chip again. The result is the only proof the change worked.
• A die change is also offered by the lab when a failed build reports that the design does not fit. It is applied only if you accept it.
• Autopilot writes DIE_AREA itself, from the design's synthesized gate count. If its build does not fit, it rebuilds once with a larger die and keeps that one in the draft. See Autopilot.