Placement
Giving every cell a position, and why where cells sit decides how fast the chip is.
Placement gives every standard cell a position in a row. It looks simple and it is one of the hardest problems in the flow, because wire length depends on it and so does speed.
Two passes#
- Global placement spreads the cells across the core, pulling connected cells towards each other and pushing crowded areas apart. Cells may overlap at this point.
- Detailed placement snaps each cell into a legal position in a row, with no overlaps.
What the tool is balancing#
- Wire length. Cells that are connected should be close. Short wires are faster and easier to route.
- Density. Cells packed too tightly leave no room for the wires above them.
- Timing. Cells on the slowest paths get priority for good positions.
Repair during placement#
Once positions are known, the tool can estimate wire delays. It then inserts buffers on long wires and resizes cells that are too weak for what they drive. This is why a build has more cells than synthesis reported.
In this lab#
The Placement phase of the build card covers global placement, pin placement, design repair and detailed placement.
Common failures#
| Symptom | Cause | What to do |
|---|---|---|
| Placement cannot finish, or reports overflow | Too much logic for the core | A larger die, or a smaller design |
| Routing fails later with congestion | Cells packed too densely in one region | A larger die, or a lower target density |
Something unclear or missing? Send feedbackSign in and use Feedback to tell us.