Combinational and sequential logic

Every digital circuit is built from two kinds of logic.

Combinational logic#

The output depends only on the inputs right now. Change an input and, a moment later, the output changes. There is no memory.

An adder, a comparator and a multiplexer are combinational.

always_comb begin
    sum = a + b;
end

Sequential logic#

The output depends on the inputs and on what happened before. Sequential logic remembers. The memory is a flip-flop: it stores one bit and updates only on a clock edge.

A counter, a register and a state machine are sequential.

always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) count <= 8'd0;
    else        count <= count + 8'd1;
end

How they fit together#

A synchronous design is flip-flops with combinational logic between them. On each clock edge every flip-flop takes a new value. Then the combinational logic works out the next values, and must finish before the next edge.

That one picture explains most of chip design. The time the logic takes sets how fast the clock can run. See Timing analysis.

Two rules that prevent most beginner bugs#

• In always_ff, use <=. In always_comb, use =.
• In always_comb, give every output a value on every path. Start the block with defaults.

If a combinational block leaves an output unassigned on some path, the tool must remember the old value, and it builds a latch: memory you did not ask for. The synthesis log says "latch inferred" when this happens.

Try it#

The Blank starter is one register: sequential logic with no combinational logic at all. Create one with nelix new reg8 --template blank, run nelix synth, and the log reports 8 cells, all flip-flops. Add q <= d + 8'd1; and the adder appears as extra gates.