RTL coding standard

A design here must work in three tools at once: the simulator, the synthesis stage and the build. These rules keep to what all three accept, and to habits that produce working silicon.

Structure#

• Start the file with ` default_nettype none ` and end it with default_nettype wire ``. An undeclared signal then becomes an error instead of a silent one-bit wire.
• The top module is named top. Declare every port with a direction, the type logic, and an explicit width.
• Name signals in lower_snake_case and parameters in UPPER_SNAKE_CASE. An active-low signal ends in _n.

Clock and reset#

• One clock, named clk, rising edge.
• One reset, named rst_n, active low and asynchronous. Every flip-flop that holds state is reset.
• Do not gate or divide the clock in logic. Use an enable.
• Do not use initial blocks or # delays to set state. On a chip, only reset sets state.

Sequential and combinational logic#

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) acc <= '0;
  else if (en) acc <= acc + product;
end

always_comb begin
  next = state;          // a default first, so no latch is inferred
  if (start) next = RUN;
end

• always_ff uses non-blocking <= only. always_comb uses blocking = only.
• Give every output of an always_comb block a default at the top.
• Every case has a default. Do not use casex.
• No combinational loops, no signal driven from two blocks, no tri-states inside the design.

Arithmetic#

• Declare signed values logic signed. Make both operands signed before a signed multiply or compare.
• Size every result on purpose. An N-bit by M-bit product is N+M bits. An accumulator needs extra bits for each doubling of the terms it can hold.
• Implement the overflow behaviour the specification states, and say which it is in a comment.

What you may use#

Allowed: logic, always_ff, always_comb, localparam, parameter, typedef enum, packed struct, generate with genvar, functions without side effects.

Not allowed: interfaces, classes, program, dynamic arrays, queues, real, assertions inside the design file.

Memory#

An array such as logic [7:0] mem [0:15] becomes flip-flops in this flow, so every stored bit costs a flip-flop and its wiring. Keep arrays small.

Before you run it#

Check that every signal is declared and driven once, that widths match on both sides of every assignment, that reset covers every state element, and that no latch is possible.