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Glossary

The words used in chip design and in this lab, in plain language.

Student 2 min read · Updated 2026-10-05

TermMeaning
RTLRegister-transfer level. A description of a design as registers and the logic between them, written in a language such as SystemVerilog
SystemVerilogThe hardware description language the lab uses for designs
ModuleA block of a design with inputs and outputs. The top one is named top
PortAn input or output of a module
Flip-flopA cell that stores one bit and updates on a clock edge
RegisterA group of flip-flops holding one value
ClockThe signal that steps the design forward
ResetThe signal that puts the design in a known starting state
TestbenchThe code that drives a design and checks what it does
SimulationRunning the design in software to see how it behaves
WaveformA picture of every signal's value over time
cocotbA framework for writing testbenches in Python
SynthesisTurning RTL into logic gates
NetlistA list of gates and the wires between them
Standard cellA ready-made logic element supplied with the process
PDKProcess design kit. The files that describe a manufacturing process to the tools
FloorplanThe die's size, its rows, pins and power grid
PlacementGiving every cell a position
Clock treeThe network of buffers that delivers the clock
RoutingDrawing the wires between cells
TimingWhether every signal arrives when it must
SetupThe requirement that data arrives early enough before a clock edge
HoldThe requirement that data stays steady just after a clock edge
SlackThe margin on a timing requirement. Negative slack is a violation
CornerOne combination of manufacturing variation, voltage and temperature
DRCDesign-rule check. Confirms the layout obeys the process's rules
LVSLayout versus schematic. Confirms the layout matches the netlist
GDSThe file format of a finished layout
DieThe rectangle of silicon the design occupies
LatencyThe number of clock cycles from an input to its output
RunOne execution of a stage, with its own id
PushWriting a file that Design Chat proposed into your project

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