DRC and LVS
The two checks at the end of the build: can it be made, and is it the design you asked for?
On this page
Design-rule check: can it be made?Layout versus schematic: is it the right circuit?Two more checksReading the resultWhat passing means, and does not meanSign-off asks two questions of the finished layout. Each has its own check.
Design-rule check: can it be made?#
A factory can only make shapes within limits: a wire must be at least so wide, two wires at least so far apart, a via must be covered by so much metal. These limits are the process's design rules. The design-rule check, DRC, tests every shape in the layout against them.
In the build it is run twice, by two tools, Magic and KLayout, as a cross-check.
Layout versus schematic: is it the right circuit?#
LVS extracts the circuit from the drawn shapes, working out which transistors exist and what is connected to what, and compares it with the netlist the layout was built from. A mismatch means the layout is not the design: a short, a missing connection, a swapped pin.
In the build it is run by Netgen.
Two more checks#
| Check | Question |
|---|---|
| Antenna | Could any long wire damage a transistor during manufacturing? |
| XOR | Do the layouts written by the two layout tools agree, shape for shape? |
Reading the result#
The chip report lists each check with its result. A clean build shows zero violations for each.
| Result | Meaning |
|---|---|
| DRC violations | A shape breaks a rule. The report names the rule and the layer |
| LVS mismatch | The layout and the netlist differ. The report names the net or device |
nelix ai drc and nelix ai lvs ask a specialist to read these results.
What passing means, and does not mean#
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