Process Lab

The Process Lab teaches how a chip is made in the factory. You learn the ten kinds of process step a fab uses, watch a chip being built, run the fab floor, and build one CMOS inverter on your own virtual wafer, in the order a real fab uses.

Open it from Process Lab in the left sidebar, or at lab.nelix.io/process-lab/. It uses your Silicon Lab sign-in, and your progress is saved to your account.

What is in it#

Each module#

Each module has four stages, shown as tabs:

• Learn: a short lesson in steps, with animations and a check at the end of each step. Learn / Engineer at the top switches between plain words and the equations with their sources. The last step has a 5-question quick check; 80 % passes it.
• Simulate: move the recipe and watch a published physics model answer, in your browser.
• Challenge: hit a fab spec on the first try, checked automatically.
• Apply to chip: where your chip's 56-step route uses this module.

Nelix Agent#

The Ask Nelix Agent buttons open Design Chat in Silicon Lab with a question already written for you. The header's Ask Nelix Agent opens the tutor beside the page; it uses your own simulation results. Both use your Nelix Agent allowance.

The premium Process Lab#

These parts are in the Process Lab for everyone.

• Your next step. The top of the Process Lab home shows one Next step with a Continue button, and your path as numbered steps with done marks. It counts everything: lessons, quick checks, simulators, challenges, Prove it checks, both films and the Fab floor parts. Back to … returns you to the last page you had open.
• Three paths. Change your path picks one: Quick tour (about 1 hour: the transistor film, three lessons, the metal-stack film, the fab team), Full course (about 8 hours: everything), or Engineer track (each module's lesson in Engineer mode and its real foundry numbers, then Prove it, then the Fab floor's control and yield parts).
• Nelix Agent on every step. A Nelix Agent bar sits under each module's tabs, under both films, on each Fab floor part, on the home and on Progress. Its question carries the step's own content: the lesson step you are reading, your simulator settings, the film step on screen. A wrong answer in a quick check or a Prove it check gets Ask Nelix Agent why, with the question, your answer and the right one. The Agent opens in its own browser tab, so you keep your place.
• Prove it. Every module has a 4-question check that tests understanding, not memory: numbers to work out (for example a lithography resolution, a wire's resistance, a Cpk), steps to put in order (the STI module, a damascene loop, an 8D), and real fab decisions. Each film has a 3-question check, and each Fab floor part has a 2-question check. The answers are marked on the server, each with an explanation, and you pass at 3 of 4. Quick-check scores are also kept on the server now, not only in your browser.
• See it in your chip. For each module: which layers in your own chip this step made, with a link to your newest finished chip build's Layout tab and to your newest analog design's Layout step, and the same layers by their names in the SKY130, GF180MCU and IHP SG13G2 kits.
• Real process numbers. For each module, real numbers from the three open process kits on the server: design rules (for example the smallest poly gate, 0.15 µm in SKY130, 0.18 µm in GF180MCU, 0.13 µm in IHP SG13G2), layer thicknesses drawn to scale, sheet resistances, gate-oxide thicknesses, density windows for CMP, threshold voltages and the wafer reject rule from IHP's process specification, and IHP's own process sequence with the module's steps highlighted. Every number names the file and line, or the PDF page and rule, it came from. The open kits do not publish an exact mask count; the page shows how many drawn layers each kit has.
• For teachers. Process Lab steps on your Assignments, class and Classes pages opens Process Lab in your class (/app/teach/process-lab). Pick a class, tick modules, films, Fab floor parts or the chip, and add an optional due date and note. Your students then see them at the top of their Process Lab home as Set by your teacher, and as their next step. The class table shows each student's progress on every step you set, including check scores, read live from the Process Lab. Download CSV saves the table.
• Build a chip, My chip. On a computer screen the cross-section and its player stay in view beside the recipe while you scroll through it, and All steps and the Lot history sit side by side below.
• Fab floor pictures. The Fab floor's header shows a working fab (wafer pods on the overhead rail, the tools, a wafer, a control chart and the yield), and each part's tab has an icon and a ✓ once its check is passed. On Yield analytics the controls sit in one panel above the results. The team opens with a fab map: a wafer travels the tool bays, each role stands where it works, and tapping a person opens their card; the day's meetings sit on one clock strip, with the details under Read what happens in each meeting. Yield task force shows the 8D path and each case's wafer map on its card. TD to HVM shows the yield ramp as a curve with its gates, and each gate card lists its first two criteria with + more for the rest. On a phone the pictures scroll sideways.
• Phones. At phone width the Ask button keeps its words, the top tabs scroll sideways, and the buttons are large enough to tap.

What it is and is not#

It is a teaching model, not calibrated to any production fab. Numbers show the right trends and typical sizes, not a specific factory's results. The numbers under Real process numbers come from the open process kits themselves.

Phones and slow connections#

Switch on Lite in the menu for still pictures instead of animations and 3D. Lessons you have opened once also work offline.