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State machines and pipelining

Two patterns that organise almost every design: doing things in order, and doing them faster.

StudentEngineer 2 min read · Updated 2026-10-05

On this page State machinesThe standard patternGetting them rightPipeliningA real caseThe cost is latency

State machines#

A finite state machine is a design that is always in exactly one of a small number of states, and moves between them on each clock according to its inputs. It is how hardware does things in order.

The guided project State machine (g4-fsm) detects the bit pattern 1011 this way: each state records how much of the pattern has been seen.

The state machine of a serial transmitter, matching the code below. A circle is a state. An arrow is a move, taken on a clock edge when its condition holds.

The standard pattern#

Two blocks: one holds the state, one works out the next.

systemverilog
typedef enum logic [1:0] {IDLE, START, DATA, STOP} state_t;
state_t state, next;

always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) state <= IDLE;
    else        state <= next;
end

always_comb begin
    next = state;                       // default: stay
    case (state)
        IDLE:    if (send)     next = START;
        START:                 next = DATA;
        DATA:    if (last_bit) next = STOP;
        STOP:                  next = IDLE;
        default:               next = IDLE;
    endcase
end

Getting them right#

  • Draw it first. Circles for states, arrows for transitions. Every state needs an arrow for every input.
  • Default to staying. next = state at the top means a forgotten case stays put instead of making a latch.
  • Reset to a known state.
  • Give states names, not numbers.

After nelix synth, the schematic shows your states as flip-flops.

Pipelining#

A design's speed is limited by its slowest path between two flip-flops. Pipelining cuts a long path in two by putting a register in the middle.

Pipelining a multiply-accumulate. The black bars are registers.
BeforeAfter
Longest pathMultiply, then addMultiply, or add
Fastest clockSlowerFaster
Latency1 clock2 clocks
Flip-flopsFewerMore

A real case#

The MAC-8 specification records exactly this trade. With the multiply and the add in one clock, the design missed timing at 10 ns at the slow corner, so the starter uses 15 ns. Its specification notes the alternative: register a and b first, at the cost of one more clock of latency.

The cost is latency#

Pipelining changes when the answer arrives. Anything that depends on the timing of the output must change too, and so must the test. That is why latency belongs in the specification, and why a pipelining change is never made silently.

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