First passing simulation
Run the starter's test, read the output line by line, and open the waveform.
On this page
Before you startRun the testRead the outputWhat a pass provesOpen the waveformIf it did not passNextA new project passes its test without any change. This page shows what "passed" looks like, so you recognise it and know what it proves.
Before you start#
You need a project. If you do not have one, follow First project.
Run the test#
In the Workspace terminal:
cd ~/project/mychip
nelix testOr press Simulate on its card on Overview. Both start the same run.
Read the output#
The last lines of a passing MAC-8 run look like this:
95.00ns INFO cocotb.top All tests passed
95.00ns INFO cocotb.regression test_top.test_mac_8bit passed
** TESTS=1 PASS=1 FAIL=0 SKIP=0 **| Part | Meaning |
|---|---|
95.00ns | Simulated time when the line was printed. The test ran the design for 95 nanoseconds |
test_top.test_mac_8bit passed | The test function named test_mac_8bit, in tb/test_top.py, finished with every check holding |
TESTS=1 PASS=1 FAIL=0 | One test ran, and it passed |
The run also gets an id, such as TST-20261005-0011. Use it to find this run again on the Runs page.
What a pass proves#
It proves that the test and the design agree. For MAC-8 the test multiplies pairs of signed 8-bit numbers and checks the running total after each one, including the largest and smallest values and a reset.
It does not prove the design is right in cases the test never tries. That is why a test is worth reading. Open tb/test_top.py and look at what it checks.
Open the waveform#
On the Simulate card choose See the waveform, or run nelix waveform.
Follow the acc row from left to right. It starts at 0, becomes 0000c (12, which is 3 times 4), then grows with each product. The full table of values is in Waveforms, reports and artefacts.
acc is 12 after 3 x 4, then 42, 28 and 43. It holds 43 while en is low, and returns to 0 when rst_n goes low. Recorded from a real simulation.If it did not pass#
A fresh starter always passes. If yours did not, the most likely cause is that the file was edited. See When a run fails.
Next#
- Change one line of
rtl/top.sv, run the test again, and watch it fail. That is the fastest way to learn what the test protects. - Go on to Synthesize and build the chip.
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