Verilator
A strict reader of your code, useful for catching mistakes before a run.
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In this labChecking your design yourselfWhat it catches that a simulator lets throughHow to use the resultVerilator is an open-source tool that compiles SystemVerilog into a fast simulation model. It is also a strict linter: it reads code and reports things that are legal and suspicious.
In this lab#
| Version | In the build: 5.018 on SKY130 and GF180MCU (OpenLane 2.3.10), 5.044 on IHP SG13G2 (LibreLane 3.0.14). In the Simulate and Synthesize image: 5.020 |
| Role | The build runs Verilator's lint as its first step (the ASAP7 learning flow does not). The Simulate stage uses Icarus Verilog, not Verilator |
Checking your design yourself#
The build lints your code before it does anything else, so a lint problem shows up at the start of Build the chip.
To run the same check by hand, first see whether the command is available in your Workspace terminal:
verilator --versionIf it prints a version, check a design with:
cd ~/project/mychip
verilator --lint-only -Wall rtl/top.svNo output means no complaints. A design written to the lab's coding standard should pass cleanly.
What it catches that a simulator lets through#
| Warning | Meaning |
|---|---|
WIDTH | The two sides of an assignment or comparison differ in width |
UNUSED | A signal is declared and never read |
UNDRIVEN | A signal is read and never assigned |
LATCH | A combinational block does not assign an output on every path |
CASEINCOMPLETE | A case does not cover every value and has no default |
BLKSEQ | A blocking assignment in sequential logic |
Each of these is a common cause of a design that simulates one way and builds another.
How to use the result#
Treat a warning as a question, not an order. Most point at real mistakes. Fix the cause in the code; do not silence the warning.
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