Synthesis failures

The design simulates and the Synthesize stage rejects it, or produces something unexpected.

StudentEngineer 1 min read · Updated 2026-10-05

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        ErrorsWarnings worth stopping forThe cell count is not what you expectedIt passed here and fails in the buildThe schematic is not drawn
      

Read reports/synth.log, or the run's log on the Runs page. The first ERROR: line is the one to act on.

Errors#

Message	Cause	Fix
`syntax error`	A construct Yosys 0.33 does not accept, though the simulator did	Rewrite it using the constructs in the RTL coding standard
`Module \top not found`	No module named `top`	Name the top module `top`
`Multiple conflicting drivers`	Two blocks assign the same signal	Assign each signal in one block only
An error on an `initial` block or a `#` delay	These describe simulation, not hardware	Remove them from the design. Use reset to set state

Warnings worth stopping for#

Message	Meaning	Fix
`Latch inferred for signal`	A combinational block does not assign that signal on every path	Give every output a default at the top of `always_comb`
A wire is used and never driven	Part of the design is disconnected	Find the missing assignment
Bits of a signal are removed as unused	Logic you wrote has no effect on any output	Check that the result is actually used

The cell count is not what you expected#

You see	Likely cause
Far fewer cells than expected	An output is not connected, so the logic behind it was removed
Zero flip-flops in a design with state	The state is never read, or the clocked block is wrong
More flip-flops than expected	An array or a wide register you did not account for. Each stored bit is one flip-flop
A very large count	A wide multiplier or a large array. Both grow quickly with width

It passed here and fails in the build#

The build synthesizes again with a newer Yosys onto real standard cells, after linting the code strictly. A warning the Synthesize stage tolerated can stop the build. Fix the cause in the code.

The schematic is not drawn#

If the Synthesize card says the schematic is not drawn yet, run:

nelix schematic

YosysThe synthesis tool: the script the Synthesize stage runs, step by step, and the two versions in use.
SynthesisHow code becomes logic gates, and what to look for in the result.