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Verilog and SystemVerilog fundamentals

The small part of the language you need to write synthesizable designs.

Student 1 min read · Updated 2026-10-05

On this page A moduleNumbersThe three ways to describe logicOperators you will useChoosing between casesNames for statesParametersWhat not to use in a design

SystemVerilog is a large language. A synthesizable design uses a small part of it. This is that part.

A module#

A design is a module with ports. In this lab the top module is named top.

systemverilog
module top (
    input  logic       clk,
    input  logic       rst_n,
    input  logic [7:0] d,
    output logic [7:0] q
);
    // logic goes here
endmodule

logic [7:0] is an 8-bit signal. Bit 7 is the most significant. Use logic for everything.

Numbers#

WrittenMeans
8'd2008 bits, decimal 200
8'hC88 bits, hexadecimal C8
4'b10104 bits, binary 1010
'0All bits 0, whatever the width

Always give a number its width. A bare 1 is 32 bits wide.

The three ways to describe logic#

systemverilog
assign done = (count == 8'd32);          // a wire that is always this

always_comb begin                        // combinational logic
    next = state;
    if (start) next = RUN;
end

always_ff @(posedge clk or negedge rst_n) begin   // flip-flops
    if (!rst_n) state <= IDLE;
    else        state <= next;
end

Operators you will use#

KindOperators
Arithmetic+ - *
Bitwise& | ^ ~
Comparison== != < > <= >=
Logical&& || !
Shift<< >> >>> (arithmetic, keeps the sign)
Join and repeat{a, b} and {4{bit}}

Choosing between cases#

systemverilog
always_comb begin
    result = '0;
    case (op)
        2'b00:   result = a + b;
        2'b01:   result = a - b;
        default: result = '0;
    endcase
end

Always include default.

Names for states#

systemverilog
typedef enum logic [1:0] {IDLE, RUN, DONE} state_t;
state_t state, next;

Parameters#

systemverilog
localparam int WIDTH = 8;
logic [WIDTH-1:0] data;

What not to use in a design#

Delays (#10), initial blocks, real, and anything that reads files belong in testbenches, not in the design. The lab's tests are written in Python, so your design file needs none of them. The full list is in the RTL coding standard.

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