Tutorial: a counter, from RTL to layout

Take the first guided project through every stage, and learn what each result means.

Student 2 min read · Updated 2026-10-05

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        ObjectiveBefore you start1. Create the project2. Read the design3. Simulate4. Open the waveform5. Synthesize6. Build the chipHow to tell it workedIf something goes wrongNext
      

Objective#

Take a working 8-bit counter through simulation, synthesis and the build, and understand each result.

Before you start#

A Nelix account, signed in.
The Workspace open. See Editor and terminal.

1. Create the project#

nelix new g1-counter --template g1-counter
cd ~/project/g1-counter

2. Read the design#

cat rtl/top.sv

systemverilog

module top (
    input  logic       clk,
    input  logic       rst_n,
    output logic [7:0] count,
    output logic       done
);
    logic en;
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            count <= 8'd0;
            en    <= 1'b0;
        end else begin
            en <= 1'b1;
            if (en) count <= count + 8'd1;
        end
    end
    assign done = (count == 8'd32);
endmodule

It counts up by one on each clock, and raises done when the count is 32.

3. Simulate#

nelix test

Expected: the run ends with

text

test_top.test_top passed
** TESTS=1 PASS=1 FAIL=0 SKIP=0 **

4. Open the waveform#

nelix waveform

Expected: find count and watch it step from 0 to 32. done goes high when it reaches 32.

The first 120 ns. count stays at 0 while rst_n is low. After reset is released, one clock passes while en is set, then count goes up by one on every rising edge. Recorded from a real simulation.

5. Synthesize#

nelix synth

Expected: the log ends with a cell count. For this design:

text

Number of cells:                 34
  $_AND_                          8
  $_DFFE_PN0P_                    8
  $_DFF_PN0_                      1
  $_NOT_                          3
  $_OR_                           7
  $_XOR_                          7

There are nine flip-flops: eight for count and one for en. The rest is the adder and the comparison with 32. nelix schematic draws them.

The first guided project, an 8-bit counter, as the synthesis tool draws it: two registers ($adff and $adffe), an adder ($add) that feeds the count back plus one, and a comparison ($eq) with 32 that drives done.

6. Build the chip#

nelix build

This takes about a minute for this design. Watch the phases on the build card on Overview.

Expected: the card shows Passed, with the cell count and area of your chip.

nelix report
nelix layout

How to tell it worked#

Simulate, Synthesize and Build the chip each show Passed on Overview.
The layout viewer shows a small block of cells in the die.

If something goes wrong#

Problem	Cause	Fix
`nelix new` says the name is taken	A project with that name exists	Use it, or choose another name: `nelix new counter2 --template g1-counter`
`nelix test` cannot find the project	You are not in the project folder	`cd ~/project/g1-counter`
The build waits before starting	Another build is running	It starts when a slot is free

Next#

Debugging a failed simulation uses the second guided project.

Verified. Simulation and synthesis run with Icarus Verilog 12.0, cocotb 2.1.0 and Yosys 0.33 on 5 October 2026. The build step was not run.

The guided projectsFive projects of rising difficulty, from running a finished design to writing a UART transmitter.
First passing simulationRun the starter's test, read the output line by line, and open the waveform.

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