Synthesize and build the chip

After a passing simulation, two more stages take the design to a layout. Run them in order.

Synthesize#

Synthesis turns the RTL into logic gates.

Press Synthesize on its card, or in the terminal:

nelix synth

When it passes, the card shows how many generic gates the design became: Yosys's own simple gates (AND, OR, XOR, flip-flops), before they are mapped to the process's cells. The chip build maps them to the process's standard cells and adds buffers, so the build's logic cells count is a different number. Both are right; they count different things.

When it passes, choose See the schematic. For MAC-8 it shows a multiplier, an adder with its feedback into the accumulator, and a register. If the card says the schematic is not drawn yet, run nelix schematic. The lab draws modules of up to 150 cells; for a bigger design draw one sub-module with nelix schematic --module <name>. The schematic page itself shows the design as a tree of modules you can step into; a design the lab prepared with the Slang reader (below) keeps its module tree too (since 31 October 2026, evening).

Build the chip#

The build places and routes the gates into a layout, using OpenLane and the SkyWater sky130A process.

Press Build the chip on its card, or in the terminal:

nelix build

MAC-8 usually finishes in a few minutes. The time limit for any build is 60 minutes. While it runs, the card shows the phase it is in. See Physical design for what each phase does.

When it passes:

• See the layout opens the layout viewer.
• Chip report shows the measured timing, area and routing.

nelix report
nelix layout

If a build reaches the time limit#

Read the card before changing anything. The layout may already be written and only the final check was cut short. Run Build the chip again when the card says the next step is to let the check finish.

A change to the die size is offered only when a failed build reports that the design does not fit, and only if you accept it. The size it offers is the one the build measured the design needs.

One clock. The clock period you save on Build settings is written to openlane/config.json and, from 31 October 2026, also to constraints/clock.sdc and config/project.toml, so the build is timed against the clock you chose. A project whose files disagree (made before that date) shows a note under the clock; saving the settings once brings them in step.

Antenna repair. Build settings has an Antenna repair choice: normal (the flow's own repair), stronger (repair wires within 30 % of the limit, protection diodes from 60 µm, 6 repair passes) and strongest (diodes from 30 µm, 10 passes). A 7,500-cell CPU needed strongest to sign off; small designs rarely need more than normal. Stronger settings add diodes, so a little area.

Large designs. After Synthesize, Build settings tells you how many gates the design has and a die size that should fit them. If you type a smaller die, Check before saving warns you before you save it (a die that is too small usually stops the build at placement). From about 10,000 gates it also warns that the build may run past the lab's 1-hour limit for one chip build; a slower clock or a lower placement density can shorten it. The build's measured results always decide.

Die too small? One automatic retry. When placement stops because the cells need more than 100 % of the die (an imported block on the blank starter's 100 × 100 µm die, for example), the lab builds once more in the same run with a die that fits the measured cell area at 40 % fill with a 30 µm ring, passed to the flow for that run only. The build log says so, the chip report says so, and openlane/config.json is not changed: keep the size from Chip build settings (Suggestions) if you want it every time.

Antenna violations: one automatic retry. Antenna violations come from the routing, not from your RTL, so when a build passes DRC and LVS but fails the antenna check, the lab builds once more in the same run with the strongest antenna repair (the Build settings "strongest" choice: margin 30, threshold 30, 10 repair passes) for that run only. The log and the chip report say so, openlane/config.json is not changed, and Build settings offers to keep the setting.

How the lab reads your design (since 31 October 2026). The chip-building flow's own Yosys reads everyday Verilog well but refuses much modern SystemVerilog. The lab decides automatically: every chip build starts with a short check by that same Yosys: if it reads your files, the chip is built from them as always; if it refuses, the lab prepares the design first with a standards-following SystemVerilog reader (Slang) and builds the plain Verilog it writes to rtl/<top>_slang.v, next to your untouched files. That file keeps your design's module tree (each module on its own; a module used several times gets a copy per instance, named <module>_<instance>), so the schematic page shows the same sub-blocks as for plain Verilog. Chip build settings (How the lab reads your design) can also force either way. The build log quotes the check's verdict, the chip report says RTL read by, and the equivalence row compares the chip with the very file it was built from. How it works and what to know: Seeds, proof limits, equivalence and the SystemVerilog subset.

The order#

For a new design the order is always the same: simulate, synthesize, build.