Icarus Verilog
The simulator behind the Simulate stage: what it does, its version here, and its common messages.
Icarus Verilog is an open-source simulator. It compiles your SystemVerilog and runs it, so the design's behaviour can be observed without building hardware.
In this lab#
| Version | 12.0 |
| Used by | The Simulate stage, nelix test |
| Language mode | SystemVerilog 2012 (the starter's Makefile passes -g2012) |
| Driven by | cocotb |
| Waveform | Written in FST format to sim_build/top.fst |
You do not run Icarus directly. nelix test runs make WAVES=1, and the project's Makefile starts Icarus with cocotb.
What it supports#
Icarus supports a large part of SystemVerilog, and not all of it. The lab's RTL coding standard lists the constructs that work in Icarus and in both synthesis tools.
Common messages#
| Message | Meaning | Fix |
|---|---|---|
rtl/top.sv:12: syntax error | The code at that line is not valid | Look at that line and the one before it. A missing ; or end is reported on the following line |
Unknown module type: foo | A module named foo is used and not defined | Check the spelling. A design here is one file, so the module must be in rtl/top.sv |
Unable to bind wire/reg/memory 'x' | A signal is used and not declared | Declare it, or fix the spelling |
error: ... is not a valid l-value | An assignment to something that cannot be assigned, such as an input | Check the port's direction |
| A width warning | The two sides of an assignment differ in width | Size the result on purpose |
What a simulator does not check#
It runs the design as written. It does not tell you whether the design can be synthesized, whether it meets timing, or whether it is correct in cases the test never tries.
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