Artefacts and reports

The files each stage produces, their formats, and how to open them.

EngineerDeveloper 2 min read · Updated 2026-10-27

        On this page
        SimulateSynthesizeBuild the chipGetting a result as dataHow long they are keptWhat is not provided
      

Each stage leaves files behind. Some stay in your project folder; the lab also keeps a copy of the important ones with the run, so a viewer can open them later.

Simulate#

File	Format	What it is	Open with
`sim_build/top.fst`	FST	The waveform: every signal over the whole test	See the waveform, `nelix waveform`
`results.xml`	XML	The test result	The stage card
The log	Text	Everything the simulator and the test printed	The Runs page, `nelix logs JOB`

Synthesize#

File	Format	What it is	Open with
`reports/synth.log`	Text	The synthesis log, ending in the cell count	`cat reports/synth.log`
`reports/top_synth.v`	Verilog	The block-level netlist	See the schematic, `nelix schematic`
`reports/top_gates.v`	Verilog	The gate-level netlist	A text editor

Build the chip#

File	Format	What it is	Open with
The layout	GDS	Every shape on every layer	See the layout, `nelix layout`
The chip report	Structured data, shown as a page	Timing at each corner, area, cells, wire length, check results	Chip report, `nelix report`

In the chip report, Utilization is the area of the placed cells without fill divided by the core area. The All placed cells, with fill line can equal the core area, because filler cells close every gap. See Waveforms, reports and artefacts for every area line. | openlane/runs/<run id>/ | Many | Every working file of the build, one folder per step | The Workspace file list |

nelix artifacts BLD-20261005-0007

lists the files kept for a build.

Getting a result as data#

Add --json to nelix report, nelix status, nelix jobs, nelix waveform, nelix schematic, nelix layout or nelix artifacts for a structured response a script can read.

How long they are kept#

The files in your project folder stay until you remove them or delete the project. Each build adds a new folder under openlane/runs/, and these are large; an old project with many builds can use much of your storage allowance.

Deleting a project removes its files and everything the lab kept for its runs.

What is not provided#

There is no public web API for fetching artefacts. They are reached through the lab's pages, the viewers and the nelix command.

Liberty, LEF, GDS and technology filesThe file formats that carry a design and a process through the flow, and what each one holds.
Waveforms, reports and artefactsOpen the waveform, the schematic, the layout and the chip report, and read a run's log.

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